11-14-2018 01:13 PM
I am preparing an experiment with a VC707 board (xc7vx485t device - ffg1761 package) and I would like to connect a 1PPS (pulse per second) signal (namely a 1 Hz signal) to USER_SMA_CLOCK_P of the board. The PPS output is CMOS from 0 to 5V, with a 20 mA maximum current. Also, it has a rise time in the vicinity of 10 ns (I believe), which in my case is very important to preserve. My question, then, is what to consider when dividing the signal voltage from 5V to 1.8V in order to feed into the FPGA input. Details in the sequel.
First of all, I am aware that the USER_SMA_CLOCK_P SMA connector is effectively a 50 ohm resistor in parallel with the FPGA input. The input, in turn, which is pin AJ32 of the FPGA, is within bank 14, which is necessarily 1.8V Vcco for this device. So I am using LVCMOS18 constraint for this input pin.
Now, the real question is what is the input impedance of the AJ32 pin in the FPGA? I've tried to look into similar questions and related documents, like SelectIO specs and package/pin specs. I see some mentions to impedance being affected by drive strength, but I am assuming this is valid when the pin is in output mode. In input mode, does it have a high impedance? Or is its resistance something like 50 ohm?
The motivation for the question is to ultimately understand whether I can use a voltage divider for the voltage conversion or whether I would need a level shifter. Can I assume a sufficiently high input impedance and then assume that it is not going to affect the divider? I was hoping to shift the voltage level with minimum degradation of rise time.
11-16-2018 02:05 PM
You'll get an idea of the input impedance from the Ccomp in the ibis model for the LVCMOS18
To be honest I would consider an IBIS simulation of this to really understand your rise time
11-16-2018 02:33 PM
I'm not sure why you think that the SMA connector has a 50 ohm resistor in it. Have you measured the 1PPS signal or are you just looking at the specifications? If you are looking at the spec sheet, I advise measuring the signal. If it is meant to drive 50 ohms, it may be a higher voltage if it's driving a higher impedance. Get a couple resistors and prototype your divider circuit before using your board.
Also, why do you want to preserve such a slow rise time? Once the signal gets into the FPGA, rise and fall times are much shorter.
11-20-2018 09:38 AM
Thanks for your response.
I might have misinterpreted, as I was just looking at specs sheet. I was assuming that the SMA connector would contain a 50 ohm in itself, whereas in reality this is only the characteristic impedance for signals whose wavelength are sufficiently smaller than the actual size of the connector/transmission line. For PPS, except for the voltage transitions, the voltage level is constant (as if it was a DC in the short term) and hence the SMA cable and connectors behave a purely resistive circuit with negligible resistance and dielectric loss. As a result, I need an external voltage divider designed with the assumption that transmission line (SMA cable) and SMA connector impedances are negligible. Is that reasonable?
To be clear regarding rise, I am looking to have a fast rise time, not a slow rise time. In the sense that the time (interval) for the signal to rise from low to high is shorter (and hence rises faster).
I guess the most important question is about the FPGA impedance, to ensure that a voltage divider circuit works properly. I will work on this now, make the divider and measure in an oscilloscope. But before plugging into the FPGA, I wanted to guarantee this is safe. I will try to understand a bit about IBIS simulation, as suggested above, but I lack experience in this domain.
Many thanks for your response once again.