Can't generate IBIS model for differential signals with Artix-7

[jcabel]

I'm trying to create an IBIS model of an Artix-7 with a DDR3 controller. My clock and strobes are differential signals at VCC = 1V5. I can synthesize and implement on the FPGA but when I use write_ibis it comes with this complain:

WARNING: [IBIS 20-793] Xilinx write_ibis has detected pins without buffer models. This may be due to either of the following cases.
(1) The latest IBIS I/O model data has not yet been installed for artix7 devices.
(2) There are no IBIS models available for use at this time.
(3) A differential port is being assigned a standard that is not a valid differential standard.

Note: If an update is made available, you may run write_ibis with the -ibs option and provide the alternate generic .ibs file.

The following signals will be listed as a no connect (NC) in the output file.

Pin Signal name IBIS model (unavailable)
--- ----------- -----------------------
C13 LDQSN DIFF_SSTL15_R_S_DT_HR
D11 UDQSN DIFF_SSTL15_R_S_DT_HR
D13 LDQSP DIFF_SSTL15_R_S_DT_HR
E11 UDQSP DIFF_SSTL15_R_S_DT_HR
P10 CKP DIFF_SSTL15_R_S_DT_HR
P11 CKN DIFF_SSTL15_R_S_DT_HR

I actually checked the 'standard' IBIS file for Artix-7 and it doesn't contain any models for differential signals at 1V5, only for 2V5 like LVDS_25.

Does this mean is not possible to create such model?

[gnarahar]

@jcabel

1. Which version of Vivado are you using?
2. What is the Complete Part#?
3. You using MIG IP to genertae the design?

[joancab]

gnarahar,

I'm using Vivado 2015.2 and the complete part is XC7A100T-2FTG256C.

I tried first with a dummy controller, just an almost empty enity with the address, control, command clocks and strobes.

Clocks and strobes are converted to differential with OBUFDS. After synthesizing, I placed the signals respecting the bank, byte groups, and diff pair pin restrictions and set the IO standard to SSTL15 for single ended signals and DIFF_SSTL15 for differential ones (clock and strobe).

I can implement the design (otherwise I wouldn't be able to run write_ibis) then write_ibis tells me it skips those ones.

I also tried by creating the interface with MIG and having a wrapper file, but had errors so I didn't spend more time that way. In my opinion all I need is pins with that IOstandard and the right ibis model to import it into hyperlynx. what is behind doesn't have to be a DDR controller at least for SI simulations, am I right?

I also tried the option -ibs and used the generic IBIS file for that part, to force copying the models from it. That gave me the same result. I checked in that IBIS file there aren't models for DIFF_SSTL, actually any model for differential signalling at 1V5, that's why I wonder if it's a question of just waiting for Xilinx or whoever to release the model. In the meantime, I'd appreciate if somebody can suggest a workaround. My goal is to assist my layout by checking SI with hyperlynx.

[gnarahar]

@joancab

DIFF_SSTL uses Single ended SSTL buffers for output. 

Where did you get the  DIFF_SSTL15_R_S_DT_HR from? Diff_Term (DT) is not available for DIFF_SSTL.

Use DIFF_SSTL15_R_S_HR and you should be able to generate the IBIS model. Hence the reason I asked if you used the MIG IP, since it will assign the correct IO Standard for the respective signals based on what memory controller you choose. 

I have attached a write_ibis generated IBIS file for your device with pinout using MIG. It uses the non_R version. You can choose the _R model for your simulations. 

[joancab]

@gnarahar

I played around for a bit with different standards and I think whenever I selected a non differential standard in the I/O planning (later written into the XDC constaints file) then it failed at implementation so I wonder how could you make it.

The text in the complain (DIFF_SSTL15_R_S_DT_HR) is different from the standard I chose in the drop down list. I think that DT was added. I'm suspecting I may have some redundant statement somewhere, maybe is not necessary the OBUFDS at all, just have the _P and _N pins.

I'll give it a go later on.

[gnarahar]

@joancab Sure. Use the .ibs file I sent you to get started with your simulations if you are in a rush and you can play around with different models since I used the "-allmodels"  argument while creating IBIS. So you will have all the models and not the only ones assigned to DDR3 pins. 

[jcabel]

Thanks, gnarahar, but what I'd like is to know how to generate them.

What I've found is:

- The IOstandard cannot be specified (in XDC file or IO Planning Layout) as DIFF_xxxx as there are no such models in the generic ibis model. This makes not possible to use OBUFDS (casts an error if single ended standards are used)

- When property DIFF_TERM is set to TRUE, model created by write_ibis has _DT_ inserted in its name (for example SSTL15 becomes SSTL15_DT_S_HR) but again, as there are no models with DT, those pins will be ignored.

- In your IBIS model, differential signals have SSTL15_F_HR model. I can obtain this by setting them as single-ended, the doubt is whether this will work for a differential signal. If it does then I wonder why all the hassle with models starting with DIFF and the DIFF_TERM property.

[joancab]

@gnarahar, hyperlynx complains about your ibis model, it expects a differnetial model for clock and strobes. I think those models are simply missing for at least Artix-7.

[gnarahar]

@joancab Will check and get back to you

[jcabel · Accepted solution]

Finally I could find a way: by creating in Vivado an I/O Planning Project, creating and placing ports defining their types (single/ differential) and IO standard. The IBIS model created can be used in hyperlynx.