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pfrancis_kraken
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Registered: ‎04-11-2019

Cannot find iSERDESE2 sites in I/O Planning project

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Hello,

As I undrestood from the 7 Series FPGA Datasheet:  " Each I/O pin possesses an 8-bit IOSERDES (ISERDES and
OSERDES)
 ".

However, when I was doing I/O planning for an XC7A15TFGG484-2.  I used the Find tool to search for sites with site type is ISERDESE2 but it returns "No Objects Found".

Did I misunderstand the datasheet?  am I searching incorrectly?  Is there anyway to confirm that the iSERDES primitives are actually available for every I/O pin on this device before having the RTL?

thanks in Advance.

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527 Views
Registered: ‎01-22-2015

@pfrancis_kraken 

Welcome to the Xilinx Forum!

As shown in the figure below from UG471, every HP-bank IO pin of the Artix-7 has an ILOGICE2 block and inside every ILOGICE2 block is an ISERDESE2.
ISERDES2_HP.jpg

Similarly, every HR-bank IO pin of the Artix-7 has an ILOGICE3 block and inside every ILOGICE3 block is an ISERDESE2.
ISERDES2_HR.jpg

In the Vivado Device view, you'll find the ILOGIC blocks next to the IO pins as shown below.
Artix7_ILOGICE3.jpg

Cheers,
Mark

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528 Views
Registered: ‎01-22-2015

@pfrancis_kraken 

Welcome to the Xilinx Forum!

As shown in the figure below from UG471, every HP-bank IO pin of the Artix-7 has an ILOGICE2 block and inside every ILOGICE2 block is an ISERDESE2.
ISERDES2_HP.jpg

Similarly, every HR-bank IO pin of the Artix-7 has an ILOGICE3 block and inside every ILOGICE3 block is an ISERDESE2.
ISERDES2_HR.jpg

In the Vivado Device view, you'll find the ILOGIC blocks next to the IO pins as shown below.
Artix7_ILOGICE3.jpg

Cheers,
Mark

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pfrancis_kraken
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Registered: ‎04-11-2019

Thanks Mark,

That I was able to find the ILOGICE3 sites as you mentioned.  I would suggest that if the SERDES block is inside of the LOGIC block then the search tool should be modified so it doesn't list the iSERDESE2 as a valid site type, or better yet, to have it listed and return the ILOGIC objects in the search results.

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Registered: ‎01-22-2015

@pfrancis_kraken 

Thanks for the suggestion - I agree!

Perhaps one of the Xilinx people will agree too - and make it happen.

Mark

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