09-03-2020 01:31 AM - edited 09-03-2020 01:32 AM
i am trying to interface a Zynq-7020 with a -1 speed grade, XC7Z020-1CLG400, with a CMOS sensor. The CMOS sensor has the following timing scheme
The interface is made of 4 LVDS data lines and one LVDS clock line all going to the same Bank on the FPGA. The data is Center-Aligned DDR Source Synchronous with a clock of 297MHz and a valid time for each data for 800 ps. As per my understanding, and following this topic, this interface cannot be captured statically with my device since my hold and setup times are clearly violated. I moved on to a Dynamic Capture scheme but it is not clear to me how to implement such algorithm. My bitrate should be 594 Mbps however the validation window of the data is way less than that. I tried to use the XAPP 1017 since my sensor is not able to send a training pattern on the data lines but i came across the following statement:
The initial delay of the master data delay is set to be nominally in the middle of the eye. The slave delay is set to be a half-bit period different (earlier or later). As a result, two samples are taken of the incoming data line, separated by a half-bit period. To work out how many taps there are in a half-bit-time, the macros have a a 16-bit input data bus that allows you to specify the bit rate directly via a 16-bit hexadecimal constant. For example, 622 Mb/s should be specified with a constant of 216'h062 (X"0622" in VHDL).
then i applied the suggested modification mentioned here to make it work as center-aligned setting my bit rate X"0594" to but with no luck. My questions right now are the following :
09-04-2020 07:32 AM
after reading some answers by @avrumw specially this one i got some better understanding on how the DPA could help improving timing so i guess my question now is around the XAPP1017 and how it might be adapt for a situation where bit valid window is different from the clock half period, i.e. unregistered output source.
Any directions on this will be really helpful.