10-21-2020 07:44 AM
We want to integrate an SSI slave interface in our sensor. I think the easiest way to do that is to use a small FPGA or CPLD.
Information about the application:
- Processor => SPI interface => CPLD/FPGA => SSI Slave
- Up to 32 bit (23/24 databits, 8 error codes)
- SSI Clockfrequency up to 2 MHz
- gray / binary coded
We already tested such a SSI interface on our large FPGA. This worked well.
The project needs about 500 logic cells.
So my question is where can I submitting my design to figure out which CPLD would be the right for me?
I think the XC2C32A would be nice.
But I'm not sure if it will fit for my application.
I can't find any usefull information about it. The datasheet has only 14 sides.
Do you have any tips for me?
If I need 500 logic cells on a FPGA how many macrocells or logic elements do I need for the CPLD?
10-21-2020 10:37 AM
10-21-2020 11:53 PM
Thanks for the answer.
I know other solutions like for example lattice FPGA iCE40UL. But I think it would be also possible to use a CPLD.
I can only find XILINX with a cheap and small CPLD like XC2C32A.
CPLD would better fit the application because they don't need so many different voltages like FPGA (also current consumption...)
So you mean it is not possible to find out more information about the XILINX CPLD?
Do you recommend do look for an other CPLD manufacturers?
Thanks for your help
10-22-2020 08:31 AM