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Registered: ‎06-26-2018

Clarification on CDR implementation

Dear to all,


I'm trying to implement a communication SerDes system without the transmission of the clock. We're talking of 4 parallel (4 bit each) lanes with a bandwidth of about 160MHz/lane.


Actually i'm a bit confused about the different implementation of the CDR techniques. Here some of my doubts:


- Assuming to use a PLL based CDR, we need to codify the data to correctly recover the clock. Based on some datasheet one of the most used technique is the 8b/10b encoding. Actually, i've found some IC for both serialization and deserializaion that instead of using 8b/10b (or other similar technique) simply add a start and a stop bit to the serialized data. How can these 2 bit guarantee the recovery of the clock? 


- Is it possibile to implement the CDR of a simple LVDS communication system using the GTX resources of the FPGA? I think the frequency is too low for it. 


- Can you suggest some AppNote to use as reference for implementing the CDR technique using the ISERDESE2 resources of the FPGA? If i'm not wrong i'll need to use some external component like the VCO for the implmentation. Am i rigth?


Thanks in advance for all your clarifications.


Best regards,



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Registered: ‎02-24-2014

I recommend these two:  XAPP523 by Marc Defossez,  and  XAPP861 by John Snow.


XAPP523 is probably a little simpler to implement than XAPP861, but either should work for your application.  The only caveat here is that your TX clock needs to be stable, and not vary more than 1000 ppm.    If you need a variable rate clock recovery, there is another core available  (non-integer data recovery unit or NIDRU),  but I don't recommend it, because it's encrypted.

Don't forget to close a thread when possible by accepting a post as a solution.
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