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Visitor
Visitor
5,837 Views
Registered: ‎08-05-2016

Clock Forwarding and differential clocks

Hi,

 

I’m using an Arty (Artix 7) and I´m interested in output a clock signal using the output pins of the board.

 

Other times I have used clock forwarding (ODDR + OBUFG) which works with single ended clocks, but this time it´s different, this time I want to output a differential clock.

 

What is the best way to output a differential clock?

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Xilinx Employee
Xilinx Employee
5,832 Views
Registered: ‎02-06-2013

Hi

 

Use ODDR+OBUFDS

Regards,

Satish

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Xilinx Employee
Xilinx Employee
5,826 Views
Registered: ‎08-01-2008

check this guide for clocking
http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
Thanks and Regards
Balkrishan
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Moderator
Moderator
5,803 Views
Registered: ‎01-16-2013

The clock forwarding should obey the ODDR mechanism.
Use OBUFDS and convert single ended clock to differential.

Thanks,
Yash
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Observer
Observer
1,220 Views
Registered: ‎08-15-2019

Dear @yashp ,

 

I have this two Ultrascale+ vcu118 and I am tryng to forward a differential clock of my master FPGA through the FMC connector 34 (see manual).

The connector 34 of the master  is connected to the connector 34 of the slave FPGA throug an FMC ribbon cable ( from Global Hitech, model FMC-TO-FMC-9-88-88).

The differential clock follows the ODDR mechanism which you mentioned below. 

On the Master, the Differential clock is fed to the output ports FMC_HPC1_LA01_CC_P and FMC_HPC1_LA01_CC_N   (both constrained to clock capable pins BC10 and BD10 with IO Standard LVDS) and on the Slave the differential clock arrives to the same named ports (this time declared as inputs) and both constrained to clock capable pins BC10 and BD10 with IO Standard LVDS.

Since according to the Ultrascale Clock Forwarding manual (ug572 , page 10) , HDGC pins can only directly drive BUFGCE and not MMCMs,   on the slave

the incoming differencial clock enters in a IBUFDS and then its single ended output is fed to a BUFGCE  (which can only take single ended inputs).

Seems like the single ended  output clock (20MHz) produced by the BUFCE is not anymore a 20MHz clock is just flat.

Indeed it is no more capable of blinking the leds on the FPGA.  While in the master it was capable. (In both FPGA there is a led blinking logic based on this clock and the logic on both FPGA is the same and works just fine on the master.

 

Both top level design are synthesized and implemented correctly without any DRC violations and generates bitstreams which I am able to flash on

on both FPGAs without issues.

I also tried on the slave to fed the incoming differential clock to an MMCM but this does not work.

Master and Slave works correctly in Behavioral simulation.

 

How i can correctly forward this 20MHz differential clock from master to slave through FMC ribbon cable ?

 

I hope you can help me .

 

Thanks a lot

Regards

 

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Observer
Observer
1,214 Views
Registered: ‎08-15-2019

*** I also tried , on the slave to connect the incoming differential clock (FMC_HPC1_LA01_P and FMC_HPC1_LA01_N)  to an MMCM and to a BUFCGE but it complains that the MMCM buffer and the BUFCGE  forms a clock cascade which cause timing issues. Anyway i ran this on the FPGAs and does not work.

 

I forgot to mention, that  in the solution which i mentioned previously (i.e.  incoming diff clock enters in the slave , then is fed to IBUFDS and then to BUFCGE ) , since there is not an MMCM which provides clock constraints, i manually added the following clock constraint:

create_clock -period 50.00 -name FMC_HPC1_LA01_CC_P -waveform {0.000 25.00} [get_ports FMC_HPC1_LA01_CC_P ]  

which specifies that on the port FMC_HPC1_LA01_CC_P there is a clock signal with period of 50ns and duty cycle of 50% (i.e . duty period 25.000ns).

Also this solution does not work.

 

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Observer
Observer
1,213 Views
Registered: ‎08-15-2019

***the aforementioned solution of using the clock constrained in the same way  which i described works just fine on Virtex-7.

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1,161 Views
Registered: ‎01-22-2015

@mik3l3_hdl 

You say that you are using HD IO pins and LVDS input/output on your Ultrascale FPGAs.  However, Table 3-1 in UG571 says that only LVDS input (and not LVDS output) is supported for HD IO.

You could use HD IO single-ended (instead of differential) to send the clock,

- or - 

maybe the FMC connector has some pin-pairs from a HP bank.  HP IO does support LVDS input/output.

Mark

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Teacher
Teacher
1,144 Views
Registered: ‎07-09-2009

one word

simulate
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Observer
Observer
1,121 Views
Registered: ‎08-15-2019

Hi markg@prosensing.com ,

first of all thanks for the prompt reply.

 

Yes , indeed I am using  HP Pin  and  i set the LVDS standard in input and output.

Now everything works.

The culprit was that   the clock signal going out of the master is a pure data  signal since it is the output of an ODDR (which has fixed inputs 1 and 0 and the input clock) so it is out of the clock distribution network of the device.

So when it reaches the slave , it is necessary to specify with a constraint (CLOCK_DEDICATED_ROUTE FALSE) that it is a data signal so it should not yet enter the device clock distribution network. Then the signal is taken in a proper IBUFDS and successive MMCM which produces as output a proper clock signal.

With this arrangement everything works fine .

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Observer
Observer
1,118 Views
Registered: ‎08-15-2019

Hi@drjohnsmith ,

 

thanks for your feedback.

Yes i simulated and works fine in behavioral.

 

Thanks

 

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