10-01-2019 03:16 AM
This is a sanity check question to see if what I think is actually correct. :)
My understanding is that if you did something that causes a BUFG clock to leave the dedicated clock net such as say routing the clock to an OP pin without ODDR, or using the clock as a flop IP that it will cause the entire clock net to leave the dedicated clock net. (i.e. All flops using this clock as a clock input will now be fed a clock from a non-dedicated clock net)
Is this correct or is the non-dedicated clock routing localized where needed?
10-01-2019 02:02 PM
Interesting question. I'd expect that for a clock tree that is mainly on dedicated clock routing driving clock ports with a small excursion somewhere then the jump onto the local routing is isolated.
I suspect it depends on the device and the design in question
10-02-2019 02:27 AM
Thanks for the answer @klumsde !
I'm pretty sure historically I was told by Xilinx staff that the whole clock would be taken off the dedicated clock net, but as you say this could be dependent on factors such as tools/family etc.
I was also told this quite a while back so my understanding could easily be WAY out of date. (i.e. Spartan 6 days and maybe early beta days of Vivado/Kintex where the SAE's may have still been drawing on ISE/S6 experience)
This is kind of where my question is coming from where I know this information is old and am probably incorrect in my understanding.
10-02-2019 02:35 AM
Would it show up on a report , the timming would be very different depending upon the solution the tools chose.
10-02-2019 03:12 AM
Yeah, I can think of a simple test case where you say run a bit of logic (e.g. a large counter) at a high speed where it's just meeting timing and then route the clock to an output pin and see what happens. I think this would "probably" show up any differences. (I will try it when I get a spare few mins)
I find it interesting that this doesnt seem to be such a strait forward question. I was seriously expecting someone to post saying. "The clock does XYZ, why are you asking such a trivial question you silly person!" :)
10-02-2019 03:53 AM
I would expect it to be different in ultrascale since you route to a root then distribute it out from this centre point. I am prepared to get proved wrong.
The test i would think of is make 2 clocks come out of the MMCM one is 1/4 the rate of the other and go on BUFG.
I would run two counters then.
Then try store the value of the fast counter in a different register using the 1/4 clock as the CE.
We'd be able to see what does with the routing then.
10-02-2019 06:50 AM
You have just proved this wonderfully
its oftern the silly questons that everyone has ignored cause its silly, that turn out to be real nut crackers.
Never stop asking.