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Visitor
Visitor
7,030 Views
Registered: ‎06-27-2016

Clock generation on the VC707 Evaluation Kit

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Hi everyone,

 

im trying to generate a single ended clock signal from the differential system clock on my VC707.

I use Vivado but i program in VHDL.

I found that i should use IBUFGDS for clock generation, but i dont get any signal. Maybe someone can help me!!!

 

The Code i use is below:

 

entity CLOCK is
       Port ( clk_n, clk_p: in std_logic;
       USER_SMA_GPIO_P : out std_logic );
end CLOCK;

 

architecture Behavioral of CLOCK is

     signal clk : std_logic;

component IBUFGDS is
     generic(IOSTANDARD : string := "LVDS");
     port(
          O : out std_logic ;
          I : in std_logic ;
          IB : in std_logic
          );

end component;


begin
     IBUFGDS_inst : IBUFGDS generic map (
     --DIFF_TERM => TRUE, -- Differential Termination
     IOSTANDARD => "LVDS_25")
     port map (
           O => clk, -- Clock buffer output
           I => clk_p, -- Diff_p clock buffer input (connect to top-level port)
           IB => clk_n -- Diff_n clock buffer input (connect to top-level port)
           );

USER_SMA_GPIO_P <= clk;

 

end Behavioral;

 

My constraintsfile looks like this:

 

set_property PACKAGE_PIN E18 [get_ports clk_n]
set_property IOSTANDARD LVDS [get_ports clk_n]
set_property DIFF_TERM TRUE [get_ports clk_n];

 

set_property PACKAGE_PIN E19 [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property DIFF_TERM TRUE [get_ports clk_p];

 

set_property PACKAGE_PIN AN31 [get_ports USER_SMA_GPIO_P]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_GPIO_P]

 

 

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Scholar
Scholar
12,529 Views
Registered: ‎06-05-2013

@xi98pisa You just have to add ODDR and forward the clock , example of this is already provided in the above post.

-Pratham

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Adventurer
Adventurer
7,024 Views
Registered: ‎02-24-2012

Hi @xi98pisa,

 

the SYSCLK on the VC707 is not LVDS. Don't specify the IOSTANDARD in the RTL code, using XDC constraints is enough.

Your constraints should look like this:

 

set_property VCCAUX_IO DONTCARE [get_ports {clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk_p}]
set_property LOC E19 [get_ports {clk_p}]

set_property VCCAUX_IO DONTCARE [get_ports {clk_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk_n}]
set_property LOC E18 [get_ports {clk_n}]

Hope that helps you.

 

Best Regards,

 

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Xilinx Employee
Xilinx Employee
7,020 Views
Registered: ‎09-05-2007

I think you need to specify ‘DIFF_SSTL15’. Here are snips from my VHDL and XDL files…

 

 

  --

  -- 200MHz differential input clock

  --

 

  clk200_input_buffer: IBUFGDS

    port map (  I => clk200_p,

               IB => clk200_n,

                O => clk200);

 

  

#

# 200MHz Differential Clock (SYSCLK)

# ----------------------------------

#

set_property PACKAGE_PIN E19 [get_ports clk200_p]

set_property PACKAGE_PIN E18 [get_ports clk200_n]

set_property IOSTANDARD DIFF_SSTL15 [get_ports clk200_p]

set_property IOSTANDARD DIFF_SSTL15 [get_ports clk200_n]

#

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor
Visitor
7,009 Views
Registered: ‎06-27-2016

Thank you for your answer, but it still doenst work. I can build a bitstream and run it on my VC707 but i get no output on my USER_SMA_GPIO.

 

I dont know where the problem is ...

Can someone give me a full example code?

Im trying to get this done for a week now.

 

Thanks in advance

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Moderator
Moderator
6,967 Views
Registered: ‎07-23-2015

@xi98pisa Can you post your implemeneted Schematic screenshot here

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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Scholar
Scholar
6,963 Views
Registered: ‎06-05-2013

@xi98pisa Use ODDR to forward clock on the USER_SMA_GPIO

 

Example code

 

IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS") ) u_clk156


(.I( USER_CLOCK_P ), .IB( USER_CLOCK_N ), .O ( userclock ) );

 

BUFG ck156 (.I( userclock ), .O( CLK156 ));

 

// Clean up clock using ODDR flip flop for best duty cycle clock output


ODDR u10 (.D1(1'b1), .D2(1'b0), .CE(1'b1), .C( CLK156 ), .Q( MYCLK ) );

 

This is optional for you as want single ended clock

 

// Use LVDS output buffer to create GTH REFCLK for SFP testing

OBUFDS u11 (.I( MYCLK ), .O( USER_SMA_CLOCK_P ), .OB( USER_SMA_CLOCK_N ) );

-Pratham

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Visitor
Visitor
6,959 Views
Registered: ‎06-27-2016

Here is my entire Code:

Design File:

CLOCK.png

Constraints File:

 

Constraints.png

I can build a bitstream and run it on my VC707, but i dont get any output.

If someone got an example of the entire clock generation with an output (the clock itself or any clock depending) in VHDL would be great. A plug & play example would be great.

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Visitor
Visitor
6,955 Views
Registered: ‎06-27-2016

The schematic:schematic.png

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Highlighted
Scholar
Scholar
12,530 Views
Registered: ‎06-05-2013

@xi98pisa You just have to add ODDR and forward the clock , example of this is already provided in the above post.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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