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Registered: ‎07-12-2019

Clock interaction failure

Hello

I had overtaken a design, it seems that there is a timing problem of some external ADC clock signals. 

I have done the clock interaction report see in the attachment. 

How could I now improve the 4 orange interactions?

I tried already with:

# AdcBitClock(x) -> AdcFrameClock(x)
set_max_delay -datapath_only -from Adc_AclkP0 -to Adc_LclkP0 5.714
set_max_delay -datapath_only -from Adc_AclkP1 -to Adc_LclkP1 5.714
set_max_delay -datapath_only -from Adc_AclkP2 -to Adc_LclkP2 5.714
set_max_delay -datapath_only -from Adc_AclkP3 -to Adc_LclkP3 5.714

But it didn't help.

clock_interaction.png
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Registered: ‎01-22-2015

@broennimann 

A clock domain is a group of circuits that all receive the same clock.  The Vivado Clock Interaction report tells you where data is being sent from one clock domain to another clock domain.   For example, if you have a register clocked by clock, CLK1, that is sending data to another register that is clocked by clock, CLK2, then this is called a clock-crossing of data from the CLK1 clock domain to the CLK2 clock domain.

You are trying to solve potential problems (orange regions) in the Clock Interaction report using constraints like the following:

set_max_delay -datapath_only -from Adc_AclkP0 -to Adc_LclkP0 5.714

The message you are giving to Vivado with constraints like this is: “I don’t now care – nor will I ever care – that *any* data is safely sent between the Adc_AclkP0 clock domain and the Adc_LclkP0 clock domain”.   I don’t think this is what you intended?

It is almost always best to solve clock-crossing problems using targeted constraints and clock-crossing circuits rather than using the blanket constraints you have attempted.

The recommendations are:

  • Comment out the constraints you have written
  • Open your implemented design and for *every* clock-crossing of data, identify exactly what data is being sent - and identify the two clocks involved.
  • If the data being sent through a clock-crossing is important to you, then use a crossing-circuit (eg. FIFO, handshake-synchronizer) and use timing constraints targeted to the crossing-circuit that allow the data to be sent safely.
  • If the data being sent through the clock-crossing is NOT important to you, then use a set_false_path constraint that is targeted to the specific clock-crossing.

If you are unsure about the handling of some specific clock-crossings then describe them to us – and maybe we can help.

Cheers,
Mark

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Registered: ‎07-12-2019

Thanks for you reply. 

The two external clocks ADC_ACLK(25MHz) and the ADC LCLK(175MHz) are coming from one ADC(ADS5294). In the ADC there is a PLL which generates these clocks synchronised to each other. In my design than the clocks are going into a SERDES unit.

Which constraint could I use to synchronise the two clocks to each other in the FPGA?

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Registered: ‎01-22-2015

@broennimann 

Please see Avrum's comments in the following post about receipt of data from an ADC that sends both a data-clock and a frame-clock.

https://forums.xilinx.com/t5/Implementation/Routable-but-not-routed-D-pin-of-ISERDESE2/m-p/780713

Cheers,
Mark

 

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Registered: ‎07-12-2019

Hy Mark,

Thanks for your useful feedback.

Unfortunately in my design the ADC signals (Data, Frame Clock and Data Clk) are spread over two banks. Therefor I think it is not possible to use IDELAY and IODELAYCTRL units like in the comment from Avrum. Is this right?

Are there other possibilities to solve that problem with the two external clocks for example with a FIFO? 

Cheers,

Manuel

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Registered: ‎01-22-2015

Manuel,

Getting data from your ADC is like the “perfect storm” of FPGA puzzles.  That is, there are some important concepts to be learned from this task and none of the concepts are trivial.  Here’s some thoughts on these concepts:

Synchronous Clocks:  If two separate clocks enter the FPGA, we should almost never consider them to be synchronous (because we cannot accurately know the phase between the two clocks).  Since we should not consider the two clocks to be synchronous then we need special clock-crossing circuits and constraints if we are going to send data from the domain of one clock to the domain of the other clock.  -more on this in the section below called “Frame Clock Trick”.

ISERDES:  The ISERDES block performs serial-to-parallel conversion of data.  For 7-Series FPGAs, you can learn basic use of ISERDES from chapter 3 of UG471(v1.10).  Figure 3-6 in UG471 describes special clocking for ISERDES that uses the BUFIO and BUFR clock buffers.  ISERDES also has a feature called Bitslip which you must learn about.

IDELAY:  The IDELAY block can be used to delay either the data or the clock coming from your ADC before they enter the ISERDES.  The use of IDELAY is often needed to make the ADC-to-FPGA interface pass timing analysis. 

ADC Interface Timing Constraints:  You will need to write constraints (set_input_delay and create_clock) for the interface between your ADC and the FPGA.  When Vivado sees these timing constraints and your placement/delay-setting for IDELAY then Vivado will tell you whether the ADC-to-FPGA interface passes timing analysis.  See Avrum’s comments <here> for more about these kind of timing constraints.

Frame Clock Trick:  The key concept for making this particular ADC-to-FPGA interface work is that the ADC frame clock, FCLK, should NOT be treated as a clock.  As Avrum explains in the 07-26-2017/11-17-2019 post to the thread I referenced previously, FCLK should be treated as data.   That is, FLCK and the data, DATI, coming from the ADC are sent to separate ISERDES.  At these ISERDES, DATI and FCLK are sampled using the ADC data clock, DCLK.  Then, as Avrum explains, you inspect the output of the ISERDES that is sampling FCLK to determine the Bitslip setting for both ISERDES.

In summary, again read Avrum’s comments (especially his 07-26-2017/11-17-2019 comments) in the thread that I referenced.  Be sure you understand why two ISERDES are used (one for DATI and one for FLCK).   Then, if needed, ask us more questions.

Cheers,
Mark