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Visitor jp93
Visitor
273 Views
Registered: ‎05-17-2018

Clock port IO placement issue in Kintex7 XC7K160TFBG-1

Hi,

I am getting below error in vivado,

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance u_mac_rxc at R21 (IOB_X0Y74) since it belongs to a shape containing instance u_mac_fpga_rgmii_gmii_ddr_mode/ODELAYE2_inst. The shape requires relative placement between u_mac_rxc and u_mac_fpga_rgmii_gmii_ddr_mode/ODELAYE2_inst that cannot be honoured because it would result in an invalid location for u_mac_fpga_rgmii_gmii_ddr_mode/ODELAYE2_inst.

Note: FPGA family - Kintex7 XC7K160TFBG-1

1) Here, R21 used as the output clock pin. This clock signal is coming from the ODELAY cell. 

2) Tool ignores the LOC and assigned some other LOC. Could not understand why R21 IOB is not suites for both clock and ODELAY placement.

3) If I remove the ODELAY cell, then the clock port is placing properly @ R21.

Please help me to resolve this issue.

 

Regards,

Jayaprakash

 

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Visitor jp93
Visitor
209 Views
Registered: ‎05-17-2018

Re: Clock port IO placement issue in Kintex7 XC7K160TFBG-1

We found that there is no ODELAY cell available near that IO PAD (R21). That is why the tool picking some other PAD to use ODELAY.

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