Clock to non CCIO pin

[skaat27]

Hi,

I am working on an ISP project, that uses a custom board that attaches to the PMOD connectors of an ARTY Z7 board and the other end to an image sensor. The problem with the custom board is that 2 pairs of MIPI signals (clk_p, clk_n and data2_p, data2_n) are swapped and as a result the clk_p/n dont go to the CCIO on the PMOD, instead the data2_P/N connect to the CCIO and clk goes to a non-CCIO pin. If i just go ahead and connect them as it is on the xdc i am able to pass implementation, but vivado wouldnt let me generate bitstream and i see this critical warning

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/mipi_csi2_rx/csi_rx_4lane_0/U0/link/clkphy/iclkdbuf at Y16 (IOB_X1Y86) since it belongs to a shape containing instance design_1_i/mipi_csi2_rx/csi_rx_4lane_0/U0/link/clkphy/iclkbufio. The shape requires relative placement between design_1_i/mipi_csi2_rx/csi_rx_4lane_0/U0/link/clkphy/iclkdbuf and design_1_i/mipi_csi2_rx/csi_rx_4lane_0/U0/link/clkphy/iclkbufio that can not be honoured because it would result in an invalid location for design_1_i/mipi_csi2_rx/csi_rx_4lane_0/U0/link/clkphy/iclkbufio. 

any suggestions as to how to proceed further? Although i can externally switch the connections using wires (doing spaghetti connection), that would be a little time consuming and needs some soldering on the custom board. I was wondering if there is a way to route the clock through non-CCIO pin itself.

TIY

Regards,

SKa

[jg_bds · Accepted solution]

It's unfortunate, but often design problems are not reported by Vivado until you get to the Write Bitstream stage. One would think that an issue that prevents bitstream creation would cause a noticeable hiccup earlier in the process... but alas. (Try forgetting to set the tech of a single IO pin sometime. Whee!)

There are occasions when missing a clock-capable pin can be forgiven. Your design, however, appears to use ICLKBUFIO--which means IO timing is critical. Clock capable pins have fixed connections to those components; not using a clock capable pin, in your case here, is preventing Vivado from routing components together. 

I don't believe there's a fix in your future. Warm-up that soldering iron.

-Joe G.

[jheslip]

you should see a critical warning earlier in the flow before the error in write_bitstream, unfortunately, there is no fix for this it is the connectivity of the device and there is no dedicated path from a non CCIO pin to a clock buffer.

[klumsde]

Hi @skaat27

This is an error at bitstream and would most likely have been a CW at the implementation step. 

As the other poster mentions there is no way around this. The clock must come from the CCIO. 

Keith