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alexkarnaukhov
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Registered: ‎09-25-2014

Clocking Wizard inverted outputs

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Hi all,

 

My main goal is to minimize power consumtion so I need to minimize count of MMCM instances in my project. Every MMCM consumes about 110mW, and this is petty big value for us.

 

My first idea was to use inverted outputs for external memory clocking. It needs 4 phase shifted clocks (0, 90, 180 and 270), so I easily can use two inverted outputs as 180 and 270 clocks.

The problem is Clocking Wizard uses inverted output INSTEAD of using another MMCM channel. So the maximum channel number is still 7.

 

Is it possible to use inverted outputs in Clocking Wizard IP simultaneously with all other clocks or I need to instantiate MMCM manualy? ClkWiz version is 5.4

clkwiz.png

(Can`t use CLKOUT1 and CLKOUT3 ! )

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alexkarnaukhov
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Registered: ‎09-25-2014

It seems that I solved my problem by instantiating MMCM manually in discrete RTL module. Also, it seems, that there really is some problems with routing/placement resources when using more than 7 outputs in "safe clock startup mode". When I tried to use all my 9 outputs with "safe clock startup"  stuff - implementation stopped with "Failed to commit 1 instances" (it was FF instance) while placement stage. With 8 "safe clock startup" outputs placement was successful but it stucks at routing trying to eliminate "overlaps" over and over.

 

Also, about "safe clock startup" - it turned out, that Microblaze work very unstable without this function (with my "very fractional" MMCM params). It just rebooting again and again several ms after start. 

 

UPD. Nope. Problem with microblaze rebooting still exists. And the biggest magic - it seems to depends on chip temperature or something such... After 10-15 minutes of my board was powered on - microblaze begin working without reboots...

UPD2. Microblaze works stable only when fpga temperature is above +45C degrees... And there is no timing violations in my project.

UPD3. Sorry, it was just floating external reset (shame).

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avrumw
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Registered: ‎01-23-2009

So I am pretty sure that this is a limitation of the MMCM (not the wizard).

 

The documentation only makes one quick reference to this fact (and it is a bit vague). In UG472, in the Introduction to the Clock Management Tile (v1.14 p. 65) it says

 

"For backward compatibility with DCMs, nine independent outputs can be selected for mapping the DCM outputs directly into the MMCM."

 

I believe this means that only 9 outputs of the MMCM can be used at any one time; one for the CLKFBOUT (which the wizard keeps "hidden") and 8 others.

 

In theory it is possible to use the output of CLKFBOUT for clocking logic, thus getting access to the 9th clock (which is, by definition, the same frequency as your input/D), although I have also read that clocking logic on this clock may increase the jitter of the MMCM (which is why it isn't discussed often, and the wizard doesn't give it as an option).

 

So, other than using CLKFBOUT (again, possibly with additional jitter on all clocks on the MMCM), you are limited to 8 outputs of the MMCM. This is probably a limitation of the routing channels around the MMCM rather than the MMCM itself.

 

Avrum

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alexkarnaukhov
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Registered: ‎09-25-2014

Just not well understand why you talking about 8 outputs, while there is only 7 outputs avialable at Clocking Wizard in MMCM mode...

 

At least now I have successful implementation of project with MMCM with 9 outputs routed: out0, out1, out1b, out2, out2b, out3, out4, out5, out6.

out0b and out3b is still unused, but i think they would route ok too.

 

So, limitation of 7 outputs at wizard is definitely not a limitation of MMCM primitive.

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anunesgu
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Registered: ‎02-09-2017

Hi @alexkarnaukhov,

 

I didn't understand exactly how many MMCM outputs do you need. Is it 9?

You can really just use 7 MMCM outputs (8 if you use the CLKFBOUT).

 

Also, what device family are you using (7-series, UltraScale, UltraScale+) ?

 

If it's US or US+, instead of configuring the 180 degree shift in the MMCM, you could use a BUFGCE_DIV which can divide and invert the output clock from a MMCM.

 

More information on the BUFGCE_DIV in the document UltraScale Architecture Libraries Guide - UG974, pg. 185.

 

This could also be valid in case you have clocks that are multiples (say 100MHz, 200MHz, 300 MHz, etc). Instead of having those as 3 MMCM outputs, you can have only one 300MHz MMCM output and then use the BUFGCE_DIV to further divide it down into other clocks.

 

I hope that helps.

 

Thanks.

Andre Guerrero

Product Applications Engineer

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alexkarnaukhov
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Registered: ‎09-25-2014

I`m using Artix-7 under Vivado 2017.3. Yes, I need 9 clocks total. Two of them are just inverted version of two other clocks. Ideally, I need the following clocks:

1)27.000MHz (need to be exactly 27)

2)150MHz (can be in range 140-150), phase shift 0

3)150MHz (can be in range 140-150), phase shift 90

4)150MHz (can be in range 140-150), phase shift 180

5)150MHz (can be in range 140-150), phase shift 270

6)190-210MHz (ref clock for IDELAYE2 primitive)

7)80MHz (can be in range 70-80MHz)

8)100MHz (can be in range 90-100MHz)

9)14MHz (can be in range 13.9-14.0MHz)

 

Such configuration can be achieved (with the precision I need) with MMCM with 100MHz input, but I can`t access to inverted pins to get (180 and 270 versions of 150MHz clock).

Yes, now I`m thinking about how I can change my project to use only 7 clocks, may be using some fabric clock dividers, or dividers based on BUFR, or using 100MHz input directly (without filtering it with mmcm).

 

But anyway, isn`t it a bug of Clocking Wizard IP to give user an inverted output INSTEAD of next clocking channel?

 

It is not very big problem to instantiate mmcm in a cuctom IP, but then I have another questions:

1)is it possible to auto calculate FREQ_HZ interface param or I need to put it in verilog code manually and change it every time I change MMCM params? Now I`m just hardcode FREQ_HZ in such a way:

(* X_INTERFACE_PARAMETER = "FREQ_HZ 80000000" *) output clock_0;   

2)Is it possible to have custom output pin names, so I could change them in block design, such I can do it with Clocking Wizard? 

 

 

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alexkarnaukhov
Explorer
Explorer
1,467 Views
Registered: ‎09-25-2014

It seems that I solved my problem by instantiating MMCM manually in discrete RTL module. Also, it seems, that there really is some problems with routing/placement resources when using more than 7 outputs in "safe clock startup mode". When I tried to use all my 9 outputs with "safe clock startup"  stuff - implementation stopped with "Failed to commit 1 instances" (it was FF instance) while placement stage. With 8 "safe clock startup" outputs placement was successful but it stucks at routing trying to eliminate "overlaps" over and over.

 

Also, about "safe clock startup" - it turned out, that Microblaze work very unstable without this function (with my "very fractional" MMCM params). It just rebooting again and again several ms after start. 

 

UPD. Nope. Problem with microblaze rebooting still exists. And the biggest magic - it seems to depends on chip temperature or something such... After 10-15 minutes of my board was powered on - microblaze begin working without reboots...

UPD2. Microblaze works stable only when fpga temperature is above +45C degrees... And there is no timing violations in my project.

UPD3. Sorry, it was just floating external reset (shame).

View solution in original post

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