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annosauer1
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Registered: ‎04-08-2015

Clocking Wizard

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I just found out the hard way, that the minimum frequency for the Clocking Wizard is 19MHz.

I have to generate among other things 32.768MHz

My OCXO is 9.8304MHz which DIV3 and MUL10 makes 32.768MHz

Does anybody have an idea how I can do that, without having to redo my PCB and use a stand alone PLL chip?

 

AJS

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alesea
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Registered: ‎05-08-2018

a.

 

I know I will be criticized for this...  You can create a delay through 6 LUT, set the KEEP / SAVEattributes so they do not get optimized out, go into an exclusive OF gate, to double the frequency.  Do that again (4X now).  Then pass to the PLL (do not use the MMCM in the clock tile).

 

Although this is asynchronous design, and never recommended (nor officially supported), I feel that the delays can be made reliable enough (hence why I suggested 6 LUT-I would instantiate 6 2 input NAND gates, with the 'spare' input tied to a signal that goes high, like a sticky terminal count bit, all 6 in tandem).  The tools will try to optimize the cascaded NAND's away, so you need to be sure that is not happening.  Reliable enough means no device will be too fast, or too slow (process corners) for this to not work

 

Then DIV by 3, multiply by 5.

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annosauer1
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Registered: ‎04-08-2015

Maybe I can answer my own question, but I have no idea if I got this right.

The Clocking Wizard (IP) has a MMCM and a PLL

The MMCM allows an input frequency of 10MHz... probably hardware reason. The PLL requires 19MHz min

If I connect my OCXO of 9.8304 it may still work

The Multiplier is 63.75 Divider is 1 and the output divider is 19.125.

This gives me 32.768MHz exact.

Do I miss something here?

 

AJS

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alesea
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Explorer
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Registered: ‎05-08-2018

a.

 

I know I will be criticized for this...  You can create a delay through 6 LUT, set the KEEP / SAVEattributes so they do not get optimized out, go into an exclusive OF gate, to double the frequency.  Do that again (4X now).  Then pass to the PLL (do not use the MMCM in the clock tile).

 

Although this is asynchronous design, and never recommended (nor officially supported), I feel that the delays can be made reliable enough (hence why I suggested 6 LUT-I would instantiate 6 2 input NAND gates, with the 'spare' input tied to a signal that goes high, like a sticky terminal count bit, all 6 in tandem).  The tools will try to optimize the cascaded NAND's away, so you need to be sure that is not happening.  Reliable enough means no device will be too fast, or too slow (process corners) for this to not work

 

Then DIV by 3, multiply by 5.

View solution in original post

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annosauer1
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Registered: ‎04-08-2015

alesa

 

Your rather pragmatic solution may actually work, but tricks like that I have not done since I was a student.

I realize that I have to "bite the bullet" and add an external PLL, meaning that I have to make a new PCB.

But your answer is correct.

 

AJS

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