04-01-2020 01:24 PM - edited 04-02-2020 05:28 AM
Hi everyone, a bit of a strange issue here. I have code that processes a video signal before outputting it in UDP packets. It was designed on Vivado 2016.3 and I've done some more recent modifications on Vivado 2019.1 and Vivado 2019.2. Unfortunately, I need to revert down to Vivado 2018.2 however even though I was able to copy the Vivado 2016.3 version and open it in Vivado 2019.1 and Vivado 2019.2 to create a working version of the project, making a copy of the original Vivado 2016.3 and opening it to upgrade the design in 2018.2 has consistently resulted in a successful synthesis, implementation, and bitstream generation - but the output is completely botched.
The IP cores I am using are 2 developed through the SelectIO Interface Wizard, 1 using the Clock Wizard, and the MIG for RAM - all of which I have verified have the same settings in 2018.2 as the other versions. Unfortunately, this is not code that I am at liberty to share.
I know that this is super generic - but if anyone has any advice on this I would appreciate it. I think I'm looking for a needle in a haystack and I'm hoping someone has a magnet for me or can point me to the right haystack.
04-05-2020 10:53 PM
In the VIVADO 2018.2 , can you elaborate more on what is not working on the hardware for Clocking Wizard , selectIO wizard and MIG IP ?
Is the behavioral and post synthesis/implementation functional and timing simulation working fine for completed design?
04-06-2020 06:32 AM
That's the biggest issue of this - all functional and timing simulations I run match the results I receive on 2016.3, 2019.1, or 2019.2 (which all work). It seems like maybe it's generating the bitstream file differently maybe? I'm not sure, but if anything was different between this version and the others at least I would have something to work off of.