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Registered: ‎05-22-2018

Communication protocol to configure DRP port of MMCM in Virtex-6 FPGA

Hi everyone,

I am trying to achieve dynamic phase shift for one of the clock outputs of MMCM_ADV primitive using its DRP port (Virtex-6 FPGA). I have gone through the application note XAPP878 that talks about MMCM dynamic reconfiguration using a module to calculate and control the write flow into CLKOUTx configuration registers of MMCM_ADV and also to calculate actual bits to write into those registers for given divide, phase and duty cycle settings using the DRP port.

However I do not want to use that module and  would like to engage an external controller to communicate with the DRP of MMCM_ADV primitive, provided, I know what the communication protocol used to communicate with the DRP port is.

So, my question is What is the communication protocol that can be used to communicate with the DRP port of MMCM in Virtex-6 FPGA? 

 

Your reply is deeply appreciated. Thanks in advance

P.S. I could not decide whether to post this question under 'Other FPGA Architectures' or 'Configuration' in 'Programmable Devices' so I posted in both.

 

-Chandrasekhar DVS

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Community Manager
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Registered: ‎08-08-2007

Hi @krishnachandrasekhar100 

 

The DRP is detailed in the Configuration UG : https://www.xilinx.com/support/documentation/user_guides/ug360.pdf Chapter 5 Dynamic Reconfiguration Port (DRP).

I would recommend using the Xapp878 wrapper around the DRP ports, otherwise you will end up building your own state machine to preform what the Xapp state machine is doing. 

 

Sandy 

Thanks,
Sandy

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664 Views
Registered: ‎05-22-2018

Hi @sandrao ,

I have used the reference design of XAPP878. In the 'mmcm_drp.v' I see that, for given divide, phase and duty cycle values(in top.v), the corresponding configuration bits are calculated and stored in configuration memory.

For the available two states in reference design of XAPP878, let us take an example

Let us say I want CLKOUT1  to have two possible phase shifts(45 and 90 degrees) w.r.t VCO clock, I will have to load corresponding values into .S1_CLKOUT1_PHASE() and .S2_CLKOUT1_PHASE() present in top.v. Then I will have to generate bitstream and dump it on the board with Virtex-6 FPGA on it.

Hence, everytime I want a different phase shift, I have to open the code of 'top.v', change the values in .S1_CLKOUT1_PHASE() and .S2_CLKOUT1_PHASE() accordingly.

 

Instead of using states, is there a way to type the new phase shift value into a terminal or something, that is converted into corresponding configuration bits and give me a new phase shift without having to load the bitstream again?

If not a terminal, is there any other user-side interface to achieve that?

 

Also another sentence in UG360, Chapter 5 DRP(Dynamic Reconfiguration Port), under Overview  'Memory bits can also be changed later through ICAP' caught my attention. Could this help me with my above mentioned requirement?

 

Thanks in advance

 

-Chandrasekhar DVS

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