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Visitor
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Registered: ‎03-14-2020

Connecting a single-ended input to two ISERDES2

Hi,

I'm using Spartan-6. I'm receiving data from single-ended asynchronous input. I want to use ISERDES2 to oversample this input at a very high sample rate. As you know -2 speed grade devices allows to achieve 945MHz. But I need x1.5 more.

My idea is to use two ISERDES2 in parallel. As I know there are two ISERDES2 primitives in IOB, so I want to connect this single-ended input to two ISERDES2, running them in 1:4 mode and feeding with opposite phase clocks. If one works on rising edge of the clock and other on falling edge I could double sample data rate. Actually for clock rate of 800MHz I could achieve 1600MHz of sample data rate which is enough for me. I tried to do this, it works in simulation as I expected, but I get mapping errors during implementation.

Is there any way to connect single-ended input to two ISERDES2 primitives? 

Thanks in advance

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: Connecting a single-ended input to two ISERDES2

I assume you using the P input for the IBUF are trying to loc the second ISERDES into the N side IO site?

You've got the map issue because there is no physical connection between the single ended IBUF and the ISERDES in the Adacent IO 

this will only work for differential IO standards as far as i know 

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Visitor
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Registered: ‎03-14-2020

Re: Connecting a single-ended input to two ISERDES2

Hi, klumsde!

Thank you for fast reply! I have a progress.



@klumsde wrote:
I assume you using the P input for the IBUF are trying to loc the second ISERDES into the N side IO site?

I made some experiments and found out that there is no map error if I connect single-ended to P input.

Also looks like this conseption works:



















As you can see I have generated two fast clocks of different polarity at the PLL side and used two BUF_PLL to drive each ISERDES2. That looks working, but I'm not pretty sure, because there is another way. I could generate a single fast clock and use single BUF_PLL to drive both ISERDES2. In this case the second ISERDES2 fast clock will be inverted locally at the very ISERDES2 clock input.

Could you please tell me which way is the best?



@klumsde wrote:
You've got the map issue because there is no physical connection between the single ended IBUF and the ISERDES in the Adacent IO 

That sounds sad. Unfortunatelly I have to oversample 8 inputs in my real design, but most of them are not routed to P-inputs on PCB. Do you want to say that there is no way to connect them to both iserdes2?

Best regards
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Visitor
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Registered: ‎03-14-2020

Re: Connecting a single-ended input to two ISERDES2

Hi, klumsde!

Thank you for fast reply! I have a progress.

 


@klumsde wrote:

I assume you using the P input for the IBUF are trying to loc the second ISERDES into the N side IO site?


I made some experiments and found out that there is no map error if I connect single-ended to P input.

Also looks like this conseption works:

oversampler.png

 

 

 

 

 

 

 

 

As you can see I have generated two fast clocks of different polarity at the PLL side and used two BUF_PLL to drive each ISERDES2. That looks working, but I'm not pretty sure, because there is another way. I could generate a single fast clock and use single BUF_PLL to drive both ISERDES2. In this case the second ISERDES2 fast clock will be inverted locally at the very ISERDES2 clock input.

Could you please tell me which way is the best?

 


@klumsde wrote:

You've got the map issue because there is no physical connection between the single ended IBUF and the ISERDES in the Adacent IO 

That sounds sad. Unfortunatelly I have to oversample 8 inputs in my real design, but most of them are not routed to P-inputs on PCB. Do you want to say that there is no way to connect them to both iserdes2?

Best regards

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Moderator
Moderator
166 Views
Registered: ‎04-18-2011

Re: Connecting a single-ended input to two ISERDES2

perhaps i am not correct about this connection. 

Its been a while since i used Spartan-6. If i were you here i'd take a look at this netlist in the FPGA editor to see the route it takes to this second ISERDES 

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