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5,060 Views
Registered: ‎05-05-2015

Constraining the output clocks of the Xilinx PCS while generating it with the vivado tool.

Hi,

 

I am using a virtex 7 FPGA and have a Gen1/Gen2 xilinx pcs generated.

 

I am getting output clocks of 500 MHz. i need them to be 125MHz/250 MHz. How can i constrain them in the GUI.

 

i give a reference clock of 100 MHz and choose 5G for the gen2 speed.  Please help.

 

These are my steps:

 

Open Vivado 2013.2 GUI
Select “Manage IP”
Create New IP Location
Select the following
Part: xc7v2000tflg1925-1
Target Language: Verilog
IP Location: <YOUR_PROJECT_LOCATION>
From the IP Catelogue
Select FPGA Features and Design IO Interfaces 7 Series FPGA Transceiver Wizard
From the 7 Series FPGA Transceiver Wizard, we can begin to customise the IP
Name the FPGA Tranceiver appropriately
Select the Line Rate, Ref Clock Selection tab
Select PCIe Gen1 Gen2 from the Protocol Drop Down Box

Enable LPM Mode
Ensure the TX and RX reference clocks are defined at 100MHz

 

thanks,

shubha.

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Moderator
Moderator
4,978 Views
Registered: ‎02-16-2010

What are the output clocks you are referring to? Can you please give there names?
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Registered: ‎05-05-2015

Hi,

They are the pipe_clock_i/mmcm_i/CLKOUT2 and pipe_clock_i/mmcm_i/CLKOUT3

thanks,

shubha

 

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Moderator
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4,892 Views
Registered: ‎02-16-2010

are you not generating the example design for the core? It should have a clock module which generates these clocks correctly to suit the core.
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Registered: ‎05-05-2015

Hi,

 

The clocks for simulation are correct.

 

However when i try to use an xdc to constrain the clocks for synthesis, the synthesis run tries to pick up an .xdc file which does not exist and gives the following error:

CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 69 of /lan/dsoft/proj_vol01/shubha/fattire/gen2_pcs_generation/pcie_gt_0/pcie_gt_0.xdc. [/lan/dsoft/proj_vol01/shubha/fattire/gen2_pcs_generation/pcie_gt_0/pcie_gt_0.xdc:69]
CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 70 of /lan/dsoft/proj_vol01/shubha/fattire/gen2_pcs_generation/pcie_gt_0/pcie_gt_0.xdc. [/lan/dsoft/proj_vol01/shubha/fattire/gen2_pcs_generation/pcie_gt_0/pcie_gt_0.xdc:70]
CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 71 of /lan/dsoft/proj_vol01/shubha/fattire/gen2_pcs_generation/pcie_gt_0/pcie_gt_0.xdc. [/lan/dsoft/proj_vol01/shubha/fattire/gen2_pcs_generation/pcie_gt_0/pcie_gt_0.xdc:71]

 

 

Acutally the synthesis script point to the right .,xdc file which hsa

 

create_clock -name pipe_userclk2_in -period 10.0 [get_pins phy_clk_i/O]
create_clock -name pipe_rxusrclk_in -period 10.0 [get_pins phy_clk_i/O]
create_clock -name pipe_rxoutclk_in -period 10.0 [get_pins phy_clk_i/O]
create_clock -name pipe_clk -period 10.0 [get_pins phy_clk_i/O]
create_clock -name pipe_pclk_in -period 10.0 [get_pins phy_clk_i/O]
create_clock -name pipe_dclk_in -period 10.0 [get_pins phy_clk_i/O]
create_clock -name pipe_userclk1_in -period 10.0 [get_pins phy_clk_i/O]

 

where the phy_clk_i is an IBUFG the output of which goes to these input clocks of the pcs.

 

Can you help me with this?

 

thanks,

shubha.

 

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Moderator
Moderator
4,831 Views
Registered: ‎02-16-2010

Can you attach a test design to check the issue?
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