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digieng
Observer
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Registered: ‎02-26-2016

Core Voltages to Power IO Banks

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Is it common or bad practice to use core voltages to power IO banks? For example, if I have an Ethernet PHY that requires 1.8V signal levels, will I be able to connect this IO bank to VCCAUX?

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gnarahar
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Moderator
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Registered: ‎07-23-2015

@digieng Yes, as mentioned in the User Guide, you can combine the power supply source for VCCO & VCCAUX if they have the same voltage. The main concern here is to take into consideration the power supply noise that can show up if the VCCO of a particular bank has lots of switching activity going on. As long as you make sure these noises don't get propagated into the power plane ( thereby affecting VCCAUX ) you should be fine. 

 

When you deviate away from recommended capacitor guidelines, we always recommend to do a PI simulation to make sure you have a good PDN on your board. 

 

If you do not have the tools, I would suggest to stick with recommend capacitor guidelines as they cover most of the user case scenarios. 

 

Last thing you need by consolidating the capacitors without PI simulation and figure out during board bring up is having lots of noise on power rails leading to loss of time and resources. 

- Giri
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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
check PCB guideline
http://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

http://www.xilinx.com/support/answers/22338.html
VCCAUX is a voltage supply for the FPGA (see the specific data sheet for the Virtex family that you are using). Xilinx recommends that all VCC and GND pins in any package be connected electrically to the board. There are no guarantees on satisfactory performance if any VCC (VCCO, VCCINT, VCCAUX ) or GND pins are not connected.
Thanks and Regards
Balkrishan
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digieng
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Registered: ‎02-26-2016

This question is in relation to an Artix-7 device. It seems that it is allowed accordin to page 35 of the '7 Series FPGAs PCB Design Guide'.

 

Powering 1.8V VCCO, VCCAUX, and VCCAUX_IO from a common PCB plane is allowed in 7 series FPGA designs. However, careful consideration must be given to power supply noise—in particular, any noise on the VCCO rail should not violate the recommended operating condition range for the VCCAUX supply.

 

Unfortunately I don't have a spectrum analyser or the software to perform an IBIS simulation. Do you advise against consolidating capacitors if I do not have these tools available? Do you recommend using all capacitors stated in table 2-1 for my device, as I do not have the tools available?

 

Sometimes a number of I/O banks are powered from the same voltage (e.g., 1.8V) and the recommended guidelines call for multiple bulk capacitors. This is also the case for VCCINT, VCCAUX, VCCAUX_IO, and VCCBRAM in the larger 7 series FPGAs. These many smaller capacitors can be consolidated into fewer (larger value) capacitors provided the electrical characteristics of the consolidated capacitors (ESR and ESL) are equal to the electrical characteristics of the parallel combination of the recommended capacitors. For most consolidations of VCCO, VCCINT, VCCAUX, VCCAUX_IO, and VCCBRAM capacitors, large tantalum capacitors with sufficiently low ESL and ESR are readily available.

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balkris
Xilinx Employee
Xilinx Employee
3,808 Views
Registered: ‎08-01-2008
check some more resource here
https://www.xilinx.com/products/design_resources/signal_integrity/resource/si_simulation.htm

I will get back to you later today
Thanks and Regards
Balkrishan
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gnarahar
Moderator
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7,038 Views
Registered: ‎07-23-2015

@digieng Yes, as mentioned in the User Guide, you can combine the power supply source for VCCO & VCCAUX if they have the same voltage. The main concern here is to take into consideration the power supply noise that can show up if the VCCO of a particular bank has lots of switching activity going on. As long as you make sure these noises don't get propagated into the power plane ( thereby affecting VCCAUX ) you should be fine. 

 

When you deviate away from recommended capacitor guidelines, we always recommend to do a PI simulation to make sure you have a good PDN on your board. 

 

If you do not have the tools, I would suggest to stick with recommend capacitor guidelines as they cover most of the user case scenarios. 

 

Last thing you need by consolidating the capacitors without PI simulation and figure out during board bring up is having lots of noise on power rails leading to loss of time and resources. 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

View solution in original post