08-10-2016 11:21 PM
- For the past week, I had done everything to resolve something I actualy saw on bench with the DAC card I had. I thought I had had designed the Serializer correctly and thought the problem was somewhere else. When I simulated (behaviorial), there were samples that were being missed. To confirm this, I put constant values and saw values being repeated within samples. I.e, it is as if mid transmission, the shift register receives a value on the CLKDIV side and then continues with the previous value.
What should have happened was what the core output produces: 100, then 101, 102, and 103.
I have thoroughly checked the bit assignment so the problem is not on the bit assignment.
I have also done the proper resetting, i.e, drive asynchronously reset low from a high, and then waited 4 CLKDIV cycles to drive the enable to the OSERDES high. In my foolishness i guess, I even at one point tried driving the OSERDES parallel data lines with outputs from SRL16s(1 cycle delay, constant). Same behavior.
Why is that that small delta, and why is the value on the serializer changing there?
What constraints does the core put to be able to simulate this correctly? (this is a simple behavioral simulation). Am I missing something here? what fundamentally have i still not understood about Serdes here?
TQ=>DDR OQ=> DDR, width=> 4, TRI_state => 4,....these were the attributes I used.
the 64 bit bus data out from device has been registered all the way till parallel inputs of Oserdes.
08-26-2016 06:44 PM
Any takers for the above issue? is it something very simple I am missing here (hence no responses yet) or is the problem confusing? Would love to get some feedback if possible. I have already went ahead and used the core to generate the interface and it works without that one sample being repeated.