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Adventurer
Adventurer
338 Views
Registered: ‎10-31-2017

Critical warnings on Zynq design

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Hello.

 

I am working on the PL side of an existing Zynq design. When I synthesize it I get 100 of critical warnings such as:

[Netlist 29-160] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. ["c:/svn/branches/Dev0.1/PL/SAR/SAR.srcs/sources_1/bd/EIT_ZYNQ/ip/EIT_ZYNQ_processing_system7_0_0/EIT_ZYNQ_processing_system7_0_0.xdc":30]

 

Below an excerpt of the xdc. 

############################################################################
# I/O STANDARDS and Location Constraints #
############################################################################

# Enet 0 / mdio / MIO[53]
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
set_property PACKAGE_PIN "C12" [get_ports "MIO[53]"]
set_property slew "slow" [get_ports "MIO[53]"]
set_property drive "8" [get_ports "MIO[53]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
# Enet 0 / mdc / MIO[52]
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
set_property PACKAGE_PIN "D10" [get_ports "MIO[52]"]
set_property slew "slow" [get_ports "MIO[52]"]
set_property drive "8" [get_ports "MIO[52]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
# GPIO / gpio[51] / MIO[51]
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
set_property PACKAGE_PIN "C10" [get_ports "MIO[51]"]
set_property slew "slow" [get_ports "MIO[51]"]
set_property drive "8" [get_ports "MIO[51]"]
set_property pullup "TRUE" [get_ports "MIO[51]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]

 

It is my understanding the project generates this script so the configurations are related to the PS side of the IP(s) used in this design. What should I do to eliminate these warnings?

 

Tool is Vivado 2016.2. IPs are up to date for this version.

 

Thanks in advance.

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1 Solution

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Xilinx Employee
Xilinx Employee
307 Views
Registered: ‎08-25-2010

回复: Critical warnings on Zynq design

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Hi @eldercosta,

Please check how do you define these MIO ports on the top wrapper?

Thanks
Simon
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2 Replies
Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎08-25-2010

回复: Critical warnings on Zynq design

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Hi @eldercosta,

Please check how do you define these MIO ports on the top wrapper?

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Adventurer
Adventurer
281 Views
Registered: ‎10-31-2017

回复: Critical warnings on Zynq design

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Hello @simon

 

It turns out the FIXED_IO pins of the ZYNQ7 IP were not connected to and interface port on the block diagram. The person who created the diagram did not bother to connect and ignored the warnings (which I do not do in my designs - zero warnings policy unless it is not possible). 

I found that when I created a new project based on the ZYNQ template.

After creating the FIXED_IO port in the bd, the related critical warnings disapeared.

Despite the lack of connection in the bd, the implementer configured correctly the MIOs. That is the reason why this issue has not been identified earlier.

I giving kudos because your post kind of guided me through the path to solve the issue.

Thank  you very much.

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