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ali99
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Registered: ‎04-08-2021

DAC LVDS DATA CAPTURE USING ZYNQ7020

Dear Community,

I AM USING ZYNQ7020. I WANT TO CAPTURE THE DATA FROM DAC VIA LVDS USING PARALLEL COMMUNICATION PROTOCOL.

I AM REALLY NEW TO THIS, CAN YOU PLEASE GUIDE ME.

ALSO IS THERE ANY POSSIBILITY THAT I CAN FIND A SAMPLE CODE OR OPEN REPOS?

BEST REGARDS

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bruce_karaffa
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Registered: ‎06-21-2017

First, do you mean DAC (digital to analog converter) or ADC (analog to digital converter)?  The DAC turns a sequence of digital words into a voltage or current.  The second turns an analog signal into digital words. 

What RTL language to you understand verilog or VHDL or do you want to use System Verilog or HLS?  Which DAC or ADC are you planning to use?  Can you post the timing diagram?  How will you connect the device to your Zynq?  Are you using a commercially produced development board or is the board a custom design?

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bruce_karaffa
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Registered: ‎06-21-2017

@ali99  Also, how many bits.  How fast are you sampling?  Is the device sending a clock with the data or is data timing based on the sample clock?

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ali99
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Registered: ‎04-08-2021

Hi Mr. Bruce,

Thanks for your help.

I am working on a project where I will use DAC. There are 16 bits. Sampling rate is 20ns. 

But at the moment I am not focusing on the actual project. I want to start learn first so I am looking for tutorials on how to do the LVDS communication with zynq7020 generally.

I am on the first step at the moment where I am learning myself and then will switch to the actual project once I learn a bit regarding this.

 

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bruce_karaffa
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Registered: ‎06-21-2017

Why do you talk about capturing data from a DAC?  You send data to a DAC.  You capture data from an ADC. 

How will you design the PL part of the Zynq?  Will you use verilog, VHDL, system verilog or HLS?  In any case, I think you need to instantiate the differential input buffers (IBUFDS) and/or output buffers (OBUFDS) in your code.  You then connect the single ended ports of the buffers to the fabric of the PL and the differential ports to the pins of the Zynq.

ali99
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Registered: ‎04-08-2021

Sending the digital data to LVDS core of DAC 9780 using Parallel communication Protocol from the DDS IP core of Zynq 7020.
Note: At the moment the scope is on PL (FPGA part) not PS (processor part) of the Zynq board.
DAC with 12 bits resolution. I will use VHLD.
Lookup-Table is for sine wave or any random wave at the moment.
Now the target is that we have one of the DDS core connected to the LVDS core which is then outputting the data to the DAC.

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