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Juanito
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Registered: ‎11-09-2020

DC bias resistors to set Vicm voltage in LVDS_25 FPGA inputs

Hello,

I am designing the interface of a LVDA_25 I/O standard input into the Artix 7 device, and I am doubting if I need to add DC bias resistors into my input lines or not.

I have been looking at the doc UG471 7 serles FPGA selectIO Resources User Guide, section: “LVDS and LVDS_25 (Low Voltage Differential Signaling)” at page 91. But is not obvious to me on its attributes table below:

Juanito_0-1604942756273.png

As it shows that it has the internal differential termination of 100ohms  “DIFF_TERM” option, but nothing about DC biased resistors.

However external DC biased resistors are recommended to be used (together with AC coupling capacitors and external diff termination) if this I/O standard is being powered by a different supply than its standard option (2.5V) as it is shown in schematic below.

Juanito_1-1604942756280.png

So I am struggling to see where I could find that internal DC biased resistors are being used when applied standard 2.5V supply. So that I know I don't need to add them. Wandering if there is a LVDA_25 I/O detailed documentation where I could find out this answer?

Kind regards,

Juan

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bruce_karaffa
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Registered: ‎06-21-2017

Can I assume that we are talking about an HR bank and not a gigabit transceiver?  If so, does the device sending data to your FPGA share a common ground?  That is, is the device on the same board or if on a different board, are the grounds connected together?  If so and the sending device has specifications compatible with the FPGA in terms of common mode voltage and differential voltage, you do not need the biasing resistors.  Also note that the diagram is specifying a clock signal.  In the case of a clock, the signal will toggle at a constant rate and probably with a 50% duty cycle.  If you use AC coupling on a signal that goes for a long period without a transition, the differential voltage will tend towards zero, giving you an unpredictable response.  Just how long a "long period" is depends on the capacitor value. 

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Juanito
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Registered: ‎11-09-2020

Hello Bruce_karffa, thank you for your reply!

Yes it is a HR bank (device is XC7A200T).

FPGA and external device are in same board and have the same ground.

External device supply is 3.3V whereas the FPGA input bank is 2.5V, so the common mode voltage is not exactly the same but there are AC coupling capacitors already on those differential lines which should get rid off this DC offset problem.

However my concern was more about how to reassure that the LVSD_25 I/O standard will supply the common mode voltage so that those differential lines will not be floating in between the capacitors and the FPGA as they will tied to the common mode voltage without the need to a add external DC bias resistors to the circuit.

I suppose a schematic of how a LVSD_25 I/O standard port is inside will help me to understand this, however I don't know where to find this information on the Xilinx documents.

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bruce_karaffa
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Registered: ‎06-21-2017

Are you sure you have a DC offset problem?  Have you looked at the data sheet for the common mode voltage of your sending device?  Have you looked at the data sheet for the Artix, (DS181) to see what the common mode voltage range is?

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Juanito
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Registered: ‎11-09-2020

Yes because external device (SY58603 with VT connected to VREF_AC) Vcm  = Vcc -1.2 = 2.1V.

However the LVDS_25 specifications (page11) say Vicm = 0.3V(min) - 1.5V(max) = 1.2V typical 

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bruce_karaffa
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Registered: ‎06-21-2017

I do wonder why you are using a CML driver to drive an LVDS input.  The differential output voltage swing 650 to 800mV is greater than the max differential input voltage of the Artix LVDS_25 input 600mV.  This may work, it may work for a while or is may cause damage.

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Juanito
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Registered: ‎11-09-2020

Do we have a better choice to drive a CML device from the FPGA than using LVDS? didn't see any CML I/O standard in the Artix7 specs.

Thank you to point out the differential voltage swing over limits, think we will use SY58605 instead in future with 500 to 650mV swing.

Any thoughts about if I would need external DC bias resistors in the FPGA LVDS input of not?

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bruce_karaffa
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Registered: ‎06-21-2017

Your question was about driving the FPGA's LVDS inputs.  Are you sending this signal to the FPGA from the SY58606 or are you sending the signal from the SY58606 to the FPGA?  If you are driving the SY58606 from the FPGA, you should be able to use the circuit on figure 6-5 of the SY58606 data sheet.

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Juanito
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Registered: ‎11-09-2020

I have actually a few SY58603s (not SY58606) connected to different pins of the FGPA (all LVDS_25 standard) some of them sending signals to FPGA but some of them receiving signals from the FPGA.

I agree with your solution for when the SY58606 is being driven by thy FPGA.

However I am still doubting how to do when the FPGA is being driven by the SY58606 as we will need AC coupling capacitors and I still don't know if I also need DC bias resistors between this capacitors and the FPGA because currently I can't find any info about it in the Xilinx documents.

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