DCM_CLKGEN in SPARTAN6

[dindea]

II am trying to include a clock generator block in my design with a SPARTAN6. I want it to generate 10MHz from the 32MHz input clock to SPARTAN6. I try with the DCM_CLKGEN component in the SPARTAN6 library. I include the DCM_CLOCKGEN in a FUB (Functional Unit Block) in ALDEC Active-HDL (i.e. in the '.bde', Block Diagram, file associated with the FUB). I connect it as in Figure 2-16 in "Spartan-6 FPGA Clocking Resources  User Guide" (UG382), i.e. all inputs except CLKIN and RST tied to GND. 

The simulation in Active-HDL just shows 'U' (Undefined)  on both used outputs. 

What do I do wrong?

[drjohnsmith]

you might want to try this on the Aldec site, The main xilinx tool for Spartan 6 is ISE, and the clock generator would be added to your code probably via a Xilinx IP GUI

https://www.aldec.com/en/support

[dindea]

This didn't give much, sorry...,

I have tried IP CoreGen in ISE 14.7 (run in Windows XP on virtual machine, VMWare). I have been succesfull when selecting DCM_SP, be it automatically (letting Coregen do the selection) or manually.

But I have not been successful when selecting DCM_CLOCKGEN, manually.

The generated VHDL files have the same structure, but the compikation in Active-HDL leaves these error messages when I try to compile the file with DCM_CLOCKGEN:

  # Error: COMP96_0078: ClockDiv_X4.vhd : (117, 20): Unknown identifier "DCM_CLKGEN".
  # Error: COMP96_0134: ClockDiv_X4.vhd : (117, 20): Cannot find component declaration.

The line causing the error is:

  dcm_clkgen_inst: DCM_CLKGEN

The file for DCM_SP has this line:

  dcm_sp_inst: DCM_SP

And this is fully accepted. The compilation works fine.

I do not find anything looking like a component declaration in any of the two files. So it seems a component declaration for DCM_SP ios "hidden somewhere". Where could I find it?

[drjohnsmith]

Re aldec dont give much (support)
sorry for that,
you get what you pay for guess,
sorry as this sounds like an aldec tools question, not much I can do here