03-22-2020 04:43 AM
II am trying to include a clock generator block in my design with a SPARTAN6. I want it to generate 10MHz from the 32MHz input clock to SPARTAN6. I try with the DCM_CLKGEN component in the SPARTAN6 library. I include the DCM_CLOCKGEN in a FUB (Functional Unit Block) in ALDEC Active-HDL (i.e. in the '.bde', Block Diagram, file associated with the FUB). I connect it as in Figure 2-16 in "Spartan-6 FPGA Clocking Resources User Guide" (UG382), i.e. all inputs except CLKIN and RST tied to GND.
The simulation in Active-HDL just shows 'U' (Undefined) on both used outputs.
What do I do wrong?
03-22-2020 09:52 AM
03-23-2020 06:12 AM
This didn't give much, sorry...,
I have tried IP CoreGen in ISE 14.7 (run in Windows XP on virtual machine, VMWare). I have been succesfull when selecting DCM_SP, be it automatically (letting Coregen do the selection) or manually.
But I have not been successful when selecting DCM_CLOCKGEN, manually.
The generated VHDL files have the same structure, but the compikation in Active-HDL leaves these error messages when I try to compile the file with DCM_CLOCKGEN:
# Error: COMP96_0078: ClockDiv_X4.vhd : (117, 20): Unknown identifier "DCM_CLKGEN".
# Error: COMP96_0134: ClockDiv_X4.vhd : (117, 20): Cannot find component declaration.
The line causing the error is:
The file for DCM_SP has this line:
And this is fully accepted. The compilation works fine.
I do not find anything looking like a component declaration in any of the two files. So it seems a component declaration for DCM_SP ios "hidden somewhere". Where could I find it?
03-23-2020 07:56 AM