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Visitor voodoo007
Visitor
240 Views
Registered: ‎10-11-2019

DCM input clock with SSC

I use the xc7k325t recover the LVDS data, but the LVDS source send the CLK with SSC,  i use this clk multi 7 to capture the data, the data is wrong. my question:

1. dose DCM can passthrough the SSC to x7 clock?

2. how much ssc the DCM can deal with?

3. should i adjust the clk phase?

 

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3 Replies
Xilinx Employee
Xilinx Employee
222 Views
Registered: ‎03-30-2016

Re: DCM input clock with SSC

Hello @voodoo007 

Since you are using Kintex-7 device, I am assuming that you are using MMCM and SelectIO.
It is mentioned in the datasheet that MMCM input clock jitter should be less than 20% of its period or 1ns at max.
K7_MMCM_input_clk_jitter.png

You may need to check if the SSC value does not exceed this jitter spec.
Probably you could test your system with SSC disabled mode before doing any other test. (adjust clk/data delay etc)

Regards
Leo

Visitor voodoo007
Visitor
132 Views
Registered: ‎10-11-2019

Re: DCM input clock with SSC

thank you for your reply.

yes i am using MMCM and SelectIO.

it can work very well without ssc.

let me check the SSC value.

if the value exceed the 20%,  do i need to adjust the  clk/data delay?  or the DCM can not work

 

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Xilinx Employee
Xilinx Employee
72 Views
Registered: ‎03-30-2016

Re: DCM input clock with SSC

Hello @voodoo007 

 

>it can work very well without ssc.

That is good to hear.

 

>let me check the SSC value.

>if the value exceed the 20%,  do i need to adjust the  clk/data delay?  or the DCM can not work

We can't guarantee MMCM will work with input clock jitter exceeds datasheet value. 
# If input clock frequency is faster than 200MHz, jitter should less than 1ns. 

 

Thanks & regards
Leo

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