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carraig
Visitor
Visitor
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Registered: ‎05-31-2016

DDR3 address pin swap

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Hi,

 

I'm using an Artix 7 with a 16 bit DDR3 interface. I can only afford to dedicate one bank (35) to the DDR3 interface. I have 16 address bits but can only find 15 to use (14 free + by grounding the CS I get one more). 

 

We can probably survive with just the 15 bits and sacrifice the extra DDR3 address space. But we thought we would try routing address pin 15 to a regular pin. Then we could select between the two sections of memory by slowly changing pin 15 say on boot. Maybe a long shot, but if it doesnt work we'll just tie address 15 low and we've lost nothing by trying.

 

However, we're having trouble in routing the board. The layout engineer has been unable to route all of the pins correctly. The best he could manage is all correct but address pins 15 and 7 are swapped. This means address 7 is not connected to a correct memory controller pin, address 15 is. 

 

My question is whether this is likely to be a problem? In memory initialisation steps etc. could this cause a problem?

 

This discussion touches the subject, but doesnt answer.

https://forums.xilinx.com/t5/Memory-Interfaces/possible-to-swap-pin-at-DDR3-memory-side/td-p/164558/page/2

 

 

Appreciate any help.

 

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gszakacs
Instructor
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Registered: ‎08-14-2007

Address pins are used to write the configuraton registers of the DDR3 memory chips.  During the time when the data to the config registers is valid on the lower address lines, upper address lines should be low to conform to requirements for unused bits that are reserved for future use.  So the only possible way you could swap address bit 7 with an upper bit is if bit seven of all configuration registers will only be written to zero.  If the upper bit you're swapping A7 with is the one you've added manually, you might be able to change this, especially if bit 7 of all config registers want to be 1 instead of 0.  If you need different values in bit 7 of different config registers, you'd need to find out how the core initializes the memory and drive your address line high or low appropriately.

 

[Edit]  I also realized that A7 is a column address bit as well as a row address, while address bits above 10 are typically only row address bits.  This means you'd also have gaps in usable address space if you swap it.

-- Gabor

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balkris
Xilinx Employee
Xilinx Employee
5,678 Views
Registered: ‎08-01-2008
check these links
https://www.xilinx.com/support/answers/33607.html
https://www.xilinx.com/support/answers/46723.html
https://forums.xilinx.com/t5/Memory-Interfaces/possible-to-swap-pin-at-DDR3-memory-side/td-p/164558
Thanks and Regards
Balkrishan
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gszakacs
Instructor
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Registered: ‎08-14-2007

Address pins are used to write the configuraton registers of the DDR3 memory chips.  During the time when the data to the config registers is valid on the lower address lines, upper address lines should be low to conform to requirements for unused bits that are reserved for future use.  So the only possible way you could swap address bit 7 with an upper bit is if bit seven of all configuration registers will only be written to zero.  If the upper bit you're swapping A7 with is the one you've added manually, you might be able to change this, especially if bit 7 of all config registers want to be 1 instead of 0.  If you need different values in bit 7 of different config registers, you'd need to find out how the core initializes the memory and drive your address line high or low appropriately.

 

[Edit]  I also realized that A7 is a column address bit as well as a row address, while address bits above 10 are typically only row address bits.  This means you'd also have gaps in usable address space if you swap it.

-- Gabor

View solution in original post