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muuu
Explorer
Explorer
7,412 Views
Registered: ‎06-17-2016

DDR3 termination(ARTIX-7 XC7A35-FGG484)

Hello,

 

 we design a ddr3 board and use Fly-by routing topology, should a 40Ω pull-up to VTT at the far end of the linebe used? we didn't find DDR Termination Regulator and 40Ω pull-up to VTT on some evaluation board, why?

 

Best regards,

Muuu

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6 Replies
watari
Professor
Professor
7,392 Views
Registered: ‎06-16-2013

Hi muuu

 

Could you show me your circuit diagram, if possible ?

 

Do you use an external DRAM chip ?

If yes, you don't need 40ohm pull-up to VTT.

Because you don't need to control CS of DRAM...

 

Thank you.

Best regards,

 

muuu
Explorer
Explorer
7,387 Views
Registered: ‎06-17-2016

Hello,

 

we use DDR3 CHIP MT41J128M16JT-125 on the board, not RDIMM or UDIMM.

 

 

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gszakacs
Instructor
Instructor
7,358 Views
Registered: ‎08-14-2007

For a fly-by topology, the address, control, and clock signals should all be terminated to Vtt at the end of the route farthest from the FPGA.  DQ and DQS signals use on-die termination and don't require board-level termination to Vtt.  The only reason a board may not implement board level termination on address or control signals is that the routes are very short (less than 1 inch typically).  Do you have a link to the evaluation board you found without Vtt termination?

-- Gabor
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muuu
Explorer
Explorer
7,326 Views
Registered: ‎06-17-2016

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trenz-al
Scholar
Scholar
7,319 Views
Registered: ‎11-09-2013

with single IC DDR component all terminations except for CLK can be ommitted fully.

6,364 Views
Registered: ‎09-11-2014

Interesting... Is this true for any data rate (1600MT/s +)? or is it for the ARTIX (800 MT/S)? Thanks.

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