04-17-2015 02:58 AM
UG583 states delays for DQ/DM to DQS, CK to address/control. It's not enough to route a DDR3-based PCB.
Where can i find full information on routing requirements?
04-17-2015 03:11 AM
UG583 is for UltraScale, please refer UG586 for 7 series design guideliness
04-17-2015 06:52 AM
The "fly-by" PCB routing is briefly described in the section "DDR3 Component PCB Routing" on page 186. I'm attaching a simplified diagram that shows the routes. Address control and clock route from the FPGA through each device in sequence and end in termination to Vtt. These signals are all unidirectional and phase-related to the clock differential output pair. Data (DQ), Data strobes (DQS) and Data mask (DM) route directly from each device to the FPGA. These are internally terminated at each end with on-die termination (ODT). Each data group (usually 8 bits) is phase related to its own DQS pair. Each group will have a different phase relationship to the outgoing clock pair, but this is taken care of during calibration.
04-18-2015 02:50 AM
Thanks for this valuable information.
But what about skew in clock differential pair (between p and n)?
What are skew requirements of ba pins?
What about reset pin?
How close can memory signals be routed to memory clocks?
How close can differential pairs be?
You said "each group will have a different phase relationship to the outgoing clock pair" but is there some limit to this difference?