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Scholar vanmierlo
Scholar
277 Views
Registered: ‎06-10-2008

[DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

I have several ISERDESE2's configured for 14 bit deserializing with IDELAYE2's to align against the incoming clock.

To use the IDELAYE2 as input to the ISERDESE2 the manual (UG471) says I should configure IOBDELAY as either IFD or BOTH. But IFD is apparently not allowed in MASTER-SLAVE configuration:

[DRC PDIL-1] Invalid Site Configuration: Invalid configuration for site ILOGIC_X0Y72. Reason: Site pin to site pin route-thru requires conflicting attribute enum values for user logic element 'ISERDESE2 in site 'ILOGIC_X0Y72'. Attribute 'IOBDELAY' is programmed to 'IFD' but needs a value of 'BOTH' for the route-thru.

However, when I choose BOTH implementation Write Bitstream DRC Required Pin gives this warning:

[DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O: The O output pin is required for IOBDELAY set BOTH or IBUF.

Yet I have no use for the O output. I only need the Q1-Q8 outputs.

Am I supposed to tie off the O output somewhere, and if yes, where and how?

Maarten

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Community Manager
Community Manager
199 Views
Registered: ‎08-08-2007

Re: [DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

Hi @vanmierlo 

 

if you are using the 14-bit deserialing you are using both the P and N side ISERDES with the width expansion. The error message is about a route-thru so I'm wondering if it is actually complaining about the N side not the P side (where you need outputs [8:13]). Can you check if the ILOGIC_X0Y72 is for the P side or the N side?

Are you using a IBUF or an IBUFDS on the P/N pair? 

You should have one IDELAY instantiated before the ISERDES's. The IDELAY on the N side would then be a route-thru. 

Can you share the snippet of code of how the IDELAY/ISERDES are instantiated? 

 

Sandy

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Scholar vanmierlo
Scholar
172 Views
Registered: ‎06-10-2008

Re: [DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

The warning is about the ISERDESE2 configured with SERDES_MODE = "MASTER". I have no idea if that is the P side or the N side. There is no warning about the ISERDESE2 configured as "SLAVE".

The input comes from lvds pairs going through an IBUFDS and an IDELAYE2.

 

	buf : IBUFDS
	port map (
		I		=> lvds_clk_p,
		IB		=> lvds_clk_n,
		O		=> unipolar_clk
	);

	dly : IDELAYE2
	generic map (
		SIGNAL_PATTERN	=> "CLOCK",
		IDELAY_TYPE	=> "VARIABLE",
		IDELAY_VALUE	=> INIT_CLK
	)
	port map (
		C		=> clk,
		CE		=> inc_delay_clk,
		LD		=> io_reset,
		LDPIPEEN	=> '0',
		REGRST		=> '0',
		CINVCTRL	=> '0',
		CNTVALUEIN	=> INIT_CLK(4 downto 0),
		INC		=> '1',
		CNTVALUEOUT	=> value_clk(4 downto 0),
		DATAIN		=> '0',
		IDATAIN		=> unipolar_clk,
		DATAOUT		=> clock_i
	);

	buf_clk : BUFIO
	port map (
		I	=> clock_i,
		O	=> clkin
	);

	clkb <= not clkin;

	div_clk : BUFR
	generic map (
		BUFR_DIVIDE => "7"
	)
	port map (
		CE	=> '1',
		CLR	=> clk_reset,
		I	=> clock_i,
		O	=> clk_div
	);

	channels : for I in 0 to WIDTH - 1 generate

		buf : IBUFDS
		port map (
			I		=> lvds_p(I),
			IB		=> lvds_n(I),
			O		=> unipolar(I)
		);

		dly : IDELAYE2
		generic map (
			SIGNAL_PATTERN	=> "CLOCK",
			IDELAY_TYPE	=> "VARIABLE",
			IDELAY_VALUE	=> INITS(I)
		)
		port map (
			C		=> clk,
			CE		=> inc_delay(I),
			LD		=> io_reset,
			LDPIPEEN	=> '0',
			REGRST		=> '0',
			CINVCTRL	=> '0',
			CNTVALUEIN	=> INITS(I)(4 downto 0),
			INC		=> '1',
			CNTVALUEOUT	=> values(I)(4 downto 0),
			DATAIN		=> '0',
			IDATAIN		=> unipolar(I),
			DATAOUT		=> data_i(I)
		);

		serdes_lsb : ISERDESE2
		generic map (
			DATA_RATE	=> "DDR",
			DATA_WIDTH	=> 14,
			INTERFACE_TYPE	=> "NETWORKING",
			IOBDELAY	=> "BOTH",
			SERDES_MODE	=> "MASTER"
		)
		port map (
			RST		=> io_reset,
			CLK		=> clkin,
			CLKB		=> clkb,
			OCLK		=> '0',
			OCLKB		=> '0',
			CLKDIVP		=> '0',
			DYNCLKSEL	=> '0',
			DYNCLKDIVSEL	=> '0',
			CE1		=> '1',
			CE2		=> '1',
			OFB		=> '0',
			D		=> '0',
			DDLY		=> data_i(I),
			SHIFTIN1	=> '0',
			SHIFTIN2	=> '0',
			SHIFTOUT1	=> shift1(I),
			SHIFTOUT2	=> shift2(I),
			CLKDIV		=> clk_div,
			BITSLIP		=> bitslip(I),
			Q1		=> data(I)(0),
			Q2		=> data(I)(1),
			Q3		=> data(I)(2),
			Q4		=> data(I)(3),
			Q5		=> data(I)(4),
			Q6		=> data(I)(5),
			Q7		=> data(I)(6),
			Q8		=> data(I)(7),
			O		=> open
		);

		serdes_msb : ISERDESE2
		generic map (
			DATA_RATE	=> "DDR",
			DATA_WIDTH	=> 14,
			INTERFACE_TYPE	=> "NETWORKING",
			IOBDELAY	=> "NONE",
			SERDES_MODE	=> "SLAVE"
		)
		port map (
			RST		=> io_reset,
			CLK		=> clkin,
			CLKB		=> clkb,
			OCLK		=> '0',
			OCLKB		=> '0',
			CLKDIVP		=> '0',
			DYNCLKSEL	=> '0',
			DYNCLKDIVSEL	=> '0',
			CE1		=> '1',
			CE2		=> '1',
			OFB		=> '0',
			D		=> '0',
			DDLY		=> '0',
			SHIFTIN1	=> shift1(I),
			SHIFTIN2	=> shift2(I),
			CLKDIV		=> clk_div,
			BITSLIP		=> bitslip(I),
			Q3		=> data(I)(8),
			Q4		=> data(I)(9),
			Q5		=> data(I)(10),
			Q6		=> data(I)(11),
			Q7		=> data(I)(12),
			Q8		=> data(I)(13),
			O		=> open
		);

	end generate;

 

 

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Community Manager
Community Manager
159 Views
Registered: ‎08-08-2007

Re: [DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

Hi @vanmierlo 

 

I took the snippet of code and implemented it in Vivado 2019.1

When I used IFD I get no DRC.

When I used Both I get the DRC, which is expected when you are not using the O port. 

[DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O: The O output pin is required for IOBDELAY set BOTH or IBUF.

I tried swapping the P and N sides to see if I could reproduce the issue but Vivado tells me that it can't assign them incorrectly 

[Vivado 12-1411] Cannot set LOC property of ports, the positive port (P-side) 'lvds_p[0]' of a differential pair cannot be placed on a negative package pin 'AM11' (IOBS). ["/home/sandrao/cases/ISERDES_Forum/project_2/project_2.srcs/constrs_1/new/Temp.xdc":285]

Do you want me to send you the testcase with your code?

 

Sandy

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Scholar vanmierlo
Scholar
151 Views
Registered: ‎06-10-2008

Re: [DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

For "IFD" the error comes in Write Bitstream. That is after Implementation already passed.

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Community Manager
Community Manager
137 Views
Registered: ‎08-08-2007

Re: [DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

Hi @vanmierlo 

 

My testcase of your code passing write_bitstream for the IFD.

What version of Vivado are you using?

Would you like me to send you my testacase?

 

Sandy

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Scholar vanmierlo
Scholar
90 Views
Registered: ‎06-10-2008

Re: [DRC REQP-107] enum_IOBDELAY_BOTH_enum_IOBDELAY_IBUF_connects_O

I'm using Vivado v2019.1 on linux. I'm targeting a Zynq 7010.

Yes, now I'm getting curious how you got this to work. So please send me your testcase.

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