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485337
Adventurer
Adventurer
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Registered: ‎05-13-2015

Data from one half to other

Hi.

 

Is it possible to route data from one half to other like on VC707 from bank 34 to bank 19? Thanks.

Data.jpg

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klumsde
Moderator
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Registered: ‎04-18-2011

Hi @485337

 

If you mean inside the fabric then why not?

Maybe give us some more detail on the what you are looking to do?

 

Keith 

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485337
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Registered: ‎05-13-2015


@klumsde wrote:

Hi @485337

 

If you mean inside the fabric then why not?

Maybe give us some more detail on the what you are looking to do?

 

Keith 


 I have data from ADC at bank 34. I need that data passed from bank 34 to bank 19, i.e. virtex7 like a buffer for data.

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klumsde
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Registered: ‎04-18-2011

Hi @485337

 

This can work. 

The thing to remember is the clocking scheme. 

if you ADC data is coming into bank 34 and it being clocking into the ISERDES with the BUFIO/BUFR (BUFIO is needed for higher data rates) combination in the documentation then these clock buffers won't be able to clock IO Logic in bank 19,

You will need to use BUFG to clock both interfaces in the two banks. 

 

 

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485337
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Registered: ‎05-13-2015

I want use for data:

pad (bank19) -> ibufds -> obufds -> pad (bank34)

 

For clock:

pad (bank19) -> ibugds -> bufg -> obufds -> pad (bank34)

 

Сan this scheme work? Or necessary use ISERDES?

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klumsde
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Registered: ‎04-18-2011

What speed is the data? what speed is the clock?

If the clock is too fast you will violate the FMAX of the BUFG. 

 

I don't know why the FPGA is used this way, it seems a waste

 

you will need to use an ODDR with its inputs tied to 1 and 0 and clocked by the BUFG to forward the clock. 

 

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485337
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Registered: ‎05-13-2015

Clock about 100 MHz.
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klumsde
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Registered: ‎04-18-2011

This should work fine then. 

 

 

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avrumw
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Registered: ‎01-23-2009

There are a number of issues with this.

 

The biggest is the delay - the delay of a combinatorial path through the FPGA is hard to constrain and is subject to large process/voltage/temperature variation. So while this can be done, it is very difficult to understand how the clock/data phase relationship on your output will relate to those on your input.

 

This is particularly true if you do what you are proposing, and run the clock through a BUFG - the BUFG will have very different delay characteristics than the data. In fact, since you are not using this clock as a "clock" there is no point in using a BUFG.

 

It is worth noting that the delay through the FPGA is going to be quite large - certainly more than 3, maybe even more than 5ns (or more depending on the I/O standards you are using).

 

As others have pointed out - this is not what an FPGA is designed to do - it does not have particularly good timing characteristics when used this way. If the "interface" is to be forwarded through the FPGA, (and you can afford some latency), then you should consider "terminating and regenerating" the interface; using the input clock to capture the incoming data, pipeline the data through the FPGA, and then regenerate the forwarded clock and forwarded data with a phase relationship that makes sense for the receiving device.

 

Avrum