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Visitor
Visitor
8,263 Views
Registered: ‎08-28-2015

Decoupling capacitor network for Artix-7 design

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Dear all,

 

I know that there have been several posts on the subject but I still did not find the answer. 

I am working on a Artix-7 () based design and I am wondering what it the best strategy for the decoupling capacitor network. I have read the UG483. However, when I look to the  Avnet Artix‐7A50T (XC7A50T‐1FTG256C) and AC701 (XC7A200T-FBG676) evaluation boards I see that the number of capacitors does not meet the guidelines.

As an axample for the XC7A200T-FBG676 Vccint, the UG483 suggests 1x680uF, 12x4.7uF, 14x0.47hF. However, on the AC701    they use  1x680uF, 2x100uF, 28x4.7uF.

Is there an explanation?

 

Regards

 

 

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Scholar
Scholar
14,280 Views
Registered: ‎02-27-2008

m,

 

The recommended capacitors (values, number) are intended for those who do not know what they will do with their board, and is a solution for most applications.  Some applications may actually require more.  Most it will be over-kill.

 

If you know what you are going to do with your board, have a power analysis provided by the tools, and know how to use a power integrity design tool, then you may build your own networks, choose your own values.  Most of our major customers do just that.

 

I cannot speak for Avnet, but they certainly do have the tools, and the skill to design the power distribution network for the intended applications they are serving with a board.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Xilinx Employee
Xilinx Employee
8,262 Views
Registered: ‎08-01-2008

 

On Package Capacitor information will most likely be published with decoupling guidelines in the 7 Series FPGAs PCB Design and Pin Planning Guide.

 

Most of the mechanical drawings and pin-lists are currently available in UG475 -7 Series FPGAs Packaging and Pinout Specifications. In addition, most current package files (.pkg) can be generated through the most current version of IDS tools using the partgen -v command.

 

 

For packages not listed in UG475 or packages listed with no drawings / pin lists / on-package capacitors, the following is just a guidance on when information will be made ready. This is subject tochange.

 

To derive estimatedschedulesof drawings / pin lists, use the following instructions:

 

 

  1. Look for Order Entry Date for Initial ES in the 7 Series Monthly Update. (On SPW)
  2. If the package in question is listed with the Order Entry Date, subtract 6 weeks from the last day of the quarter or month listed
  3. The resulting date is an estimate you can share with the field contact or EA customer.
  4. If the package in question is not listed with the Order Entry Date, subtract 6 weeks from the last day of the quarter / month in the General ES column
  5. The resulting date is an estimate you can share with the field contact or EA customer.

For example, if you are looking for XC2000T FL1925, look for the Virtex-7 Silicon updates section of the 7 series Monthly update. Since the Initial ES column does not list this package, go with the date in the General ES column. Subtract 6 weeks from the last date of CYQ2'12 (note: this was from the July 2011 update).

 


you can also check
http://www.xilinx.com/support/answers/43204.html
The user guide provides all details about how to connect unused GT I/Os. A floating I/O is needed on development boards because any GT I/O must be accessible for tests and measurements. If a particular GT is not used, this seems to be in contrast with UG recommendation.

The user guide also suggests to ground unused GT I/Os because this is a "good design" practice. Of course, an I/O that is floating or (that is a similar condition) connected to decoupling capacitor will not break just because it is floating.

Thanks and Regards
Balkrishan
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Visitor
Visitor
8,261 Views
Registered: ‎08-28-2015

Hello,

 

thanks for your reply. However, I can't find the answer to my question.

 

Cheers

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Xilinx Employee
Xilinx Employee
8,258 Views
Registered: ‎08-01-2008

I think information given in UG483

 

http://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

Thanks and Regards
Balkrishan
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Visitor
Visitor
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Registered: ‎08-28-2015

Exaclty, when I look at tthis table and then I check the two eval boards schematics I realise that the number of capacitors used does not match:

 

1.jpg

2.jpg

The same for the AC701 Eval board.

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Scholar
Scholar
8,245 Views
Registered: ‎06-05-2013

@matte_dc Evaluation board schematics are for just a refrence, i would recommend you to please follow UG483 recommendations no matter whats their in schmatics.

 

if you would like to know more please open a service request on this issue.

-Pratham

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Xilinx Employee
Xilinx Employee
8,228 Views
Registered: ‎07-31-2012

Hi,

 

To understand why the difference in the actual implementation, you can read through the theory  - http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf

 

The main aim is to cover different frequency ranges where the impedance is the least. In general the recommendation is to use the supported capacitors given in the UG. However you have to do the final power integrity simulations, to check how the impedance profile looks like. 

Sometimes if the capacitances are not available, you can use alternate capacitors but there are recommendations for these too.

Check the foot note of Table 2-4 of the below link

 

http://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Scholar
Scholar
14,281 Views
Registered: ‎02-27-2008

m,

 

The recommended capacitors (values, number) are intended for those who do not know what they will do with their board, and is a solution for most applications.  Some applications may actually require more.  Most it will be over-kill.

 

If you know what you are going to do with your board, have a power analysis provided by the tools, and know how to use a power integrity design tool, then you may build your own networks, choose your own values.  Most of our major customers do just that.

 

I cannot speak for Avnet, but they certainly do have the tools, and the skill to design the power distribution network for the intended applications they are serving with a board.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Professor
Professor
8,223 Views
Registered: ‎08-14-2007

@pratham wrote:

@matte_dc Evaluation board schematics are for just a refrence, i would recommend you to please follow UG483 recommendations no matter whats their in schmatics.

 

if you would like to know more please open a service request on this issue.


Very good advice!  Often the reference designs were based on boards used to "bring up" new parts before they were fully characterized.  The numbers in the User Guide tables are based on the latest characterization data.

-- Gabor
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Visitor
Visitor
8,221 Views
Registered: ‎08-28-2015

Thank you all for your answers.

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Explorer
Explorer
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Registered: ‎11-19-2010

PDN decoupling is not a simple equation. as it has been pointed here it depends on the board usage, as well as the geometry and stack-up. Even with the same usage, two boards may behave differently. On top of that, capacitors, when we use them for decoupling, the least important parameter is their capacitance. We look for small ESR and ESL, basically. And there is also some extra inductance depending on the vias location next to each capacitor. 

summing it all up, the way I'd suggest for decoupling is to use some PDN analysis simulation tool. If that's not available, common sense rules may produce a working board after a few loops.

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