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nhs
Visitor
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1,214 Views
Registered: ‎03-29-2018

Delaying a clock input

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I have a global clock input as follows:

 

module MySystem(
	[...]
	input wire PIN_PCB_CLK,
	[...]
	);

[...]
wire CLK_PCB; // this is used as a clock and other clocks are derived from it
wire clk_1x; // buffered version of input clock PIN_PCB_CLK
wire clk_2x; // optional 2x division

// buffer input
IBUFG clk_pcb_buf(
	.O(clk_1x),
	.I(PIN_PCB_CLK)
);

// clock divider
clk_wiz_v3_6 clk_wiz_v3_6(.CLK_IN1(clk_1x), .CLK_OUT1(clk_2x));

// select either 1x or 2x clock for CLK_PCB
// cfg1 is a control register
BUFGMUX clk_pcb_mux(
	.O(CLK_PCB), // Clock MUX output
	.I0(clk_1x), // Clock0 input
	.I1(clk_2x), // Clock1 input
	.S(cfg1[0]) // Clock select input
);

To account for relative timing outside of the FPGA, I would like to relatively delay everything that happens within the FPGA. The clock can be up to ~80-100 MHz so adding a delay in the ns range (maybe even below) would be great.

 

What is the simplest way to achieve this?

 

Similarly as the S input of the BUFGMUX in the above code, I would like to have this delay software programmable via a configuration register.

 

I heard about IODELAY2 but I cannot find any information how to instantiate it properly.

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pthakare
Moderator
Moderator
1,469 Views
Registered: ‎08-08-2017

Hi @nhs

 

You can use the digital clock manager to phase shift a clock signal, either by a fixed fraction of a clock period or by incremental amounts.

You can get the more detailing of this in Spartan-6 clocking user guide 

https://www.xilinx.com/support/documentation/user_guides/ug382.pdf  -> Page  59.

 

IODELAY2 primitives are use to delay the data signals. you can find the IODELAY2 detailing in spartan-6 selectIO user guide 

https://www.xilinx.com/support/documentation/user_guides/ug381.pdf   -> page 72

 

and instantiations template in Spartan-6 Libraries user guide

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf  -> page 137

 

-------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and accept as solution

------------------------------------------------------------------------------------------------------

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

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2 Replies
pthakare
Moderator
Moderator
1,470 Views
Registered: ‎08-08-2017

Hi @nhs

 

You can use the digital clock manager to phase shift a clock signal, either by a fixed fraction of a clock period or by incremental amounts.

You can get the more detailing of this in Spartan-6 clocking user guide 

https://www.xilinx.com/support/documentation/user_guides/ug382.pdf  -> Page  59.

 

IODELAY2 primitives are use to delay the data signals. you can find the IODELAY2 detailing in spartan-6 selectIO user guide 

https://www.xilinx.com/support/documentation/user_guides/ug381.pdf   -> page 72

 

and instantiations template in Spartan-6 Libraries user guide

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf  -> page 137

 

-------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and accept as solution

------------------------------------------------------------------------------------------------------

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

nhs
Visitor
Visitor
1,134 Views
Registered: ‎03-29-2018

Great! I just modified my clz_wiz appropriately:

 

wire PSDONE;
clk_wiz_v3_6 clk_wiz_v3_6(
	// Clock in ports
	.CLK_IN1(PIN_PCB_CLK),  // IN
	// Clock out ports
	.CLK_OUT1(clk_1x),   	// OUT
	.CLK_OUT2(clk_2x),   	// OUT
	// Dynamic phase shift ports
	.PSCLK(ti_clk),			// IN
	.PSEN(PSEN),				// IN
	.PSINCDEC(PSINCDEC),		// IN
	.PSDONE(trigger_out[0]) // OUT
);

BUFGMUX clk_pcb_mux(
	.O(CLK_PCB), // Clock MUX output
	.I0(clk_1x), // Clock0 input
	.I1(clk_2x), // Clock1 input
	.S(cfg1[0]) // Clock select input
);

 

which internally uses the clock manager. Unfortunately I do not really have a way to verify at this moment but it seems the right thing so I mark as solved :) Thanks again!