07-18-2018 09:49 PM
Does anyone know:
1. What is the range of the delay (in ns/ps) which the Kintex 7 410T FPGA can delay output data with respect to
an input clock?
2. What is the range of the jitter which the Kintex 7 410T FPGA adds to output data?
07-18-2018 10:24 PM
please go through the following user guide. (idelay,odelay)
there is fixed tap delay which can be selected. (max 32 levels)
07-19-2018 02:22 AM
The datasheet states that outputs can be delayed by up to 32 increments of 78/52 or 39 ps which is fine for my application.
I'm still searching for how much jitter would be present in the outputs and by how much this would be reduced when HIGH_PERFORMANCE mode is enabled.