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rajanbedi
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Registered: ‎03-13-2017

Delaying output data from a Kintex 7 410T FPGA

 

Hello,

 

Does anyone know:

 

1. What is the range of the delay (in ns/ps) which the Kintex 7 410T FPGA can delay output data with respect to

an input clock?

 

2. What is the range of the jitter which the Kintex 7 410T FPGA adds to output data?

 

Thank you,

Rajan.

 

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rajeshkhanna
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Registered: ‎08-09-2013

Hi,

please go through the following user guide. (idelay,odelay)

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

there is fixed tap delay which can be selected. (max 32 levels)

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rajanbedi
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Registered: ‎03-13-2017

The datasheet states that outputs can be delayed by up to 32 increments of 78/52 or 39 ps which is fine for my application.

 

I'm still searching for how much jitter would be present in the outputs and by how much this would be reduced when HIGH_PERFORMANCE mode is enabled.

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