I am implementing a 1 to 10 deserializer based on the application note XAPP1017 for Kintex-7. My system should be able to read data from 64 LVDS lines synchronized with two LVDS clocks, 32 lines by each clock, in 800Mbps DDR. I should work with a pre-designed board and the main proposed architecture (the following figure) by the application note leads to routing error indicating that BUFR outputs can drive the IDELAYE2 and ISERDESE2 in the same clock regions while in my design, not all the LVDS lines synched with one clock are
I am not sure if I could do any other things, but I did the following modifications as can be seen in the figure. I removed the clock part of the proposed architecture and instantiated an MMCM for every input clock, and the desired clocks including 400MHz, 200MHz, and 80MHz are generated by the MMCM.
However, it does not work properly and I am getting corrupted data. I have checked the tap values of the IDELAYE2s and they are running in the middle of the eye. The calculated tap values by the deskew state machine sound correct since by setting the phase-detection off and go with these tap values (but fixed), then it is completely ok.
What could be the problem? Is this implementation basically correct or erroneous?