09-19-2014 06:44 AM
I'm implementing a custom design FPGA board using Virtex-7 FPGA.
Using reference from the stackup on VC707, I realised that there are 3 different impedance control for this design. For example, PCIe 2.0 is likely using 85R differential impedance and LVDS clock are using 100R differential impedance.
Is there any documentation that stated the design consideration for using 80/85/100 differential impedance and what are the types of signals that need the impedance? Similarly for the single-ended signal using 40/50 ohms.
Also, for FMC connector, what are the considerations for length matching the HPC (LA, HA, HB) signals?
09-19-2014 07:14 AM
Have a look at the PCB.01#02 of the below link.
For 6 layer it is pointed as 100 Ohm and 8/10 layer boards are pointed to 85Ohm diff imp.
09-19-2014 07:23 AM
Regarding the FMC board design.
I believe you should look at how it is done with existing cards.
http://www.xilinx.com/support/documentation/boards_and_kits/ug538.pdf - FMC XM101 card user guide.