Sir, I want to know how do we decide the values for timing constraints in xilinx vivado? Is it necessary to give false path and multicycle exception for every design in vivado?
An over constraind designis as bad / worse than a under constraind one.
Things you need to constrain,
Clocks into the FPGA .
if you have more than one clock into the FPGA, then any false paths into the fpga need to be marked.
Io pin placments.
After that, its down to you companies design rules and what your aiming for.
I'd normaly put set up and hold times on all the IO,
and mark any asyncronous clock crosssing paths,
then look at the timmings your getting.