cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
bryankerr1986
Visitor
Visitor
2,179 Views
Registered: ‎06-17-2018

Differential Clock Input fed into IBUFDS cannot set LOC property of ports

Hello,

 

I am using the xa7a50tcsg325 FPGA and I can't get past this error...

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance IBUFDS_inst at B6 (IPAD_X1Y16) since it belongs to a shape containing instance CLK_N. The shape requires relative placement between IBUFDS_inst and CLK_N that can not be honoured because it would result in an invalid location for CLK_N. ["C:/Users/Bryan/Documents/Projects/VHDL/PicoEVB/Sample-Projects/blinky/imp/Design_Files/io.xdc":81]

 

This is my code:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity blinky is
   port
   (
   CLK_P     : in  std_logic;
   CLK_N     : in  std_logic;
   RST_N     : in  std_logic;
   EN_CLK_N  : out std_logic;
   LED1      : out std_logic;
   LED2      : out std_logic;
   LED3      : out std_logic
   );
end entity blinky;

architecture rtl of blinky is

signal led_i   : std_logic;
signal cntr    : unsigned(23 downto 0);
signal clk_i   : std_logic;
signal clk_100 : std_logic;

begin

   EN_CLK_N <= '0';

   blinky_proc : process(clk_100, RST_N)
   begin
      if rising_edge(clk_100) then
         if (RST_N='0') then
            cntr  <= x"FFFFFF";
            led_i <= '0';
         else
            cntr <= cntr - 1;
            if (cntr = (cntr'range => '0')) then
               cntr  <= x"FFFFFF";
               led_i <= not(led_i);
            end if;
         end if;
      end if;
   end process blinky_proc;
   
   LED1 <= led_i;
   LED2 <= led_i;
   LED3 <= led_i;
   
   
   -- IBUFDS: Differential Input Buffer
   -- 7 Series
   -- Xilinx HDL Libraries Guide, version 2012.2
   IBUFDS_inst : IBUFDS
   generic map
   (
   DIFF_TERM    => FALSE, -- Differential Termination
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD   => "DEFAULT")
   port map
   (
   O  => clk_i, -- Buffer output
   I  => CLK_P, -- Diff_p buffer input (connect directly to top-level port)
   IB => CLK_N  -- Diff_n buffer input (connect directly to top-level port)
   );
   
   -- BUFG: Global Clock Simple Buffer
   -- 7 Series
   -- Xilinx HDL Libraries Guide, version 2012.2
   BUFG_inst : BUFG
   port map
   (
   O => clk_100, -- 1-bit output: Clock output
   I => clk_i -- 1-bit input: Clock input
   );

end rtl;

This is my .xdc file:

 

##-----------------------------------------------------------------------------
##
## (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##-----------------------------------------------------------------------------
##
## Project    : The Xilinx PCI Express DMA
## File       : xilinx_xdma_pcie_x0y0.xdc
## Version    : $IpVersion
##-----------------------------------------------------------------------------
###############################################################################
# User Configuration
# Link Width   - x1
# Link Speed   - gen2
# Family       - artix7
# Part         - xc7a50t
# Package      - csg325
# Speed grade  - -2
# PCIe Block   - X0Y0
###############################################################################

#########################################################################################################################
# PCIE Core Constraints
#########################################################################################################################

###############################################################################
# Pinout and Related I/O Constraints
###############################################################################
# SYS reset (input) signal.  The sys_reset_n signal is generated
# by the PCI Express interface (PERST#).
set_property PACKAGE_PIN A10 [get_ports RST_N]
set_property IOSTANDARD LVCMOS33 [get_ports RST_N]
set_property PULLDOWN true [get_ports RST_N]

# SYS clock 100 MHz (input) signal. The CLK_P and sys_clk_n
# signals are the PCI Express reference clock. 
set_property PACKAGE_PIN B6 [get_ports CLK_P]

## PCIe x1 link
#set_property PACKAGE_PIN G4 [get_ports pcie_mgt_rxp]
#set_property PACKAGE_PIN G3 [get_ports pcie_mgt_rxn]
#set_property PACKAGE_PIN B2 [get_ports pcie_mgt_txp]
#set_property PACKAGE_PIN B1 [get_ports pcie_mgt_txn]

# MGT Loopback
#set_property PACKAGE_PIN C4 [get_ports loop_mgt_rxp]
#set_property PACKAGE_PIN C3 [get_ports loop_mgt_rxn]
#set_property PACKAGE_PIN D2 [get_ports loop_mgt_txp]
#set_property PACKAGE_PIN D1 [get_ports loop_mgt_txn]

###############################################################################
# Timing Constraints
###############################################################################

create_clock -period 10.000 -name sys_clk [get_ports CLK_P]
#set_property CLOCK_DEDICATED_ROUTE FALSE[get_nets CLK_IBUF]

###############################################################################
# Physical Constraints
###############################################################################

# Input reset is resynchronized within FPGA design as necessary
set_false_path -from [get_ports RST_N]

#########################################################################################################################
# End PCIe Core Constraints
#########################################################################################################################


###############################################################################
# NanoEVB, PicoEVB common I/O
###############################################################################

set_property PACKAGE_PIN V14 [get_ports {LED3}]
set_property PACKAGE_PIN V13 [get_ports {LED2}]
set_property PACKAGE_PIN V12 [get_ports {LED1}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED3}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED2}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED1}]
set_property PULLUP true [get_ports {LED3}]
set_property PULLUP true [get_ports {LED2}]
set_property PULLUP true [get_ports {LED1}]
set_property DRIVE 8 [get_ports {LED3}]
set_property DRIVE 8 [get_ports {LED2}]
set_property DRIVE 8 [get_ports {LED1}]

# EN_CLK_N is active low clock request for M.2 card to
# request PCI Express reference clock
set_property PACKAGE_PIN A9 [get_ports EN_CLK_N]
set_property IOSTANDARD LVCMOS33 [get_ports EN_CLK_N]
set_property PULLDOWN true [get_ports EN_CLK_N]

## Auxillary I/O Connector
## auxio[0] - conn pin 1
## auxio[1] - conn pin 2
## auxio[2] - conn pin 4
## auxio[3] - conn pin 5
## Note: These I/O may be re-purposed to use with XADC as analog inputs
#set_property PACKAGE_PIN A14 [get_ports auxio_tri_io[0]]
#set_property PACKAGE_PIN A13 [get_ports auxio_tri_io[1]]
#set_property PACKAGE_PIN B12 [get_ports auxio_tri_io[2]]
#set_property PACKAGE_PIN A12 [get_ports auxio_tri_io[3]]
#set_property IOSTANDARD LVCMOS33 [get_ports auxio_tri_io[0]]
#set_property IOSTANDARD LVCMOS33 [get_ports auxio_tri_io[1]]
#set_property IOSTANDARD LVCMOS33 [get_ports auxio_tri_io[2]]
#set_property IOSTANDARD LVCMOS33 [get_ports auxio_tri_io[3]]

################################################################################
## PicoEVB-specific I/O
## Digital IO on PCIe edge connector (PicoEVB Rev.D and newer)
################################################################################
#set_property PACKAGE_PIN K2 [get_ports di_edge[0]]
#set_property PACKAGE_PIN K1 [get_ports di_edge[1]]
#set_property PACKAGE_PIN V2 [get_ports do_edge[0]]
#set_property PACKAGE_PIN V3 [get_ports do_edge[1]]
#set_property IOSTANDARD LVCMOS33 [get_ports di_edge[0]]
#set_property IOSTANDARD LVCMOS33 [get_ports di_edge[1]]
#set_property IOSTANDARD LVCMOS33 [get_ports do_edge[0]]
#set_property IOSTANDARD LVCMOS33 [get_ports do_edge[1]]

################################################################################
## NanoEVB-specific I/O
################################################################################
## Serial input/output
## Available on NanoEVB only!
#set_property IOSTANDARD LVCMOS33 [get_ports RxD]
#set_property IOSTANDARD LVCMOS33 [get_ports TxD]
#set_property PACKAGE_PIN V17 [get_ports RxD]
#set_property PACKAGE_PIN V16 [get_ports TxD]
#set_property PULLUP true [get_ports RxD]
#set_property OFFCHIP_TERM NONE [get_ports TxD]


###############################################################################
# Additional design / project settings
###############################################################################

# High-speed configuration so FPGA is up in time to negotiate with PCIe root complex
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Any Ideas? Thanks! i've been stuck for hours (new to Vivado from Quartus)

 

Bryan

0 Kudos
Reply
4 Replies
avrumw
Guide
Guide
2,166 Views
Registered: ‎01-23-2009

By instantiating an IBUFDS you are telling the tool that the input is differential. However, your XDC is not setting the IOSTANDARD of the CLK_P/CLK_N, and since it is not set, the tool assumes the default, which is LVCMOS25 - a single ended standard.

 

I suspect that if you properly configure the IOSTANDARD to the appropriate differential standard (LVDS or LVDS_25 as appropriate for the bank) this error will go away.

 

Avrum

0 Kudos
Reply
bryankerr1986
Visitor
Visitor
2,127 Views
Registered: ‎06-17-2018

Unfortunately that did not work...

 

I made the following changes to the code:

   -- IBUFDS: Differential Input Buffer
   -- 7 Series
   -- Xilinx HDL Libraries Guide, version 2012.2
   IBUFDS_inst : IBUFDS
   generic map
   (
   DIFF_TERM    => FALSE, -- Differential Termination
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD   => "LVDS_25")
   port map
   (
   O  => clk_i, -- Buffer output
   I  => CLK_P, -- Diff_p buffer input (connect directly to top-level port)
   IB => CLK_N  -- Diff_n buffer input (connect directly to top-level port)
   );

and to the xdc:

# SYS clock 100 MHz (input) signal. The CLK_P and sys_clk_n
# signals are the PCI Express reference clock. 
set_property PACKAGE_PIN B6 [get_ports CLK_P]
set_property PACKAGE_PIN B5 [get_ports CLK_N]
set_property IOSTANDARD LVDS_25 [get_ports CLK_P]
set_property IOSTANDARD LVDS_25 [get_ports CLK_N]

I still get the same error...

I found the following information about these pins (if it helps):

Device/Package xc7a50tcsg325 12/3/2013 11:23:33                                                                                                   
                                                                                                        
Pin  Pin Name                      Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
B6   MGTREFCLK1P_216               NA                 216   NA            NA                  GTP       NA
B5   MGTREFCLK1N_216               NA                 216   NA            NA                  GTP       NA

CLK_P and CLK_N are input pins from a PCIe interface.

0 Kudos
Reply
bryankerr1986
Visitor
Visitor
2,118 Views
Registered: ‎06-17-2018

I fixed the problem...

 

Instead of instantiating this:

 

-- IBUFDS: Differential Input Buffer
-- 7 Series
-- Xilinx HDL Libraries Guide, version 2012.2
IBUFDS_inst : IBUFDS
generic map
(
DIFF_TERM    => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD   => "LVDS_25")
port map
(
O  => clk_i, -- Buffer output
I  => CLK_P, -- Diff_p buffer input (connect directly to top-level port)
IB => CLK_N  -- Diff_n buffer input (connect directly to top-level port)
);

I instantiated this:

 

u_ibufds_gte2 : IBUFDS_GTE2
port map
(
CEB => '0',
ODIV2 => open,
O  => clk_i, -- 
I  => CLK_P, -- 
IB => CLK_N  -- 
);

Don't ask me why it works because I have no idea...

0 Kudos
Reply
gnarahar
Moderator
Moderator
2,072 Views
Registered: ‎07-23-2015

@bryankerr1986 


Don't ask me why it works because I have no idea...


Simple :). Because you are using GTP, you need to use IBUFDS_GTE2. Below pic from UG482 Ref Clk input structure that explains it

 

IBUFDS_GTE.JPG

 


I found the following information about these pins (if it helps):

Device/Package xc7a50tcsg325 12/3/2013 11:23:33                                                                                                   
                                                                                                        
Pin  Pin Name                      Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
B6   MGTREFCLK1P_216               NA                 216   NA            NA                  GTP       NA
B5   MGTREFCLK1N_216               NA                 216   NA            NA                  GTP       NA

CLK_P and CLK_N are input pins from a PCIe interface.


This was the key for you to mention. IBUFDS is only valid for PL part of the fabric. For GTP in your device, you need to use the respective GT primitives. I would suggest you use UG482 as a guide. 
- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------