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Explorer
Explorer
5,769 Views
Registered: ‎12-18-2014

Differential clock out to gtx refclk in via cleaner pll

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Hello,

i want to feed out a differential clock signal to a cleaner pll and the output of that pll is connected to the gtx refclk input. 

Which primitives do i need to feed a diff. clk out.

 

Kintex7 

Vivado 2015.1

 

Thanks

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Professor
Professor
10,258 Views
Registered: ‎08-14-2007

If the clock you want to drive out is on a buffered clock net, then the best way is to instantiate an ODDR followed by an OBUFDS.  There should be examples of this if you search documentation for "clock forwarding."  You should also make sure that the LVDS output of the FPGA gives sufficient drive level to the jitter cleaner, and that the jitter cleaner provides sufficient drive for the GTX reference clock input.  Usually cap coupling is required in the GTX clock path, and depending on the drive style (LVPECL, CML... ) of the jitter cleaner you may need resistors to pull down and/or terminate the signal.

-- Gabor

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Xilinx Employee
Xilinx Employee
5,751 Views
Registered: ‎07-21-2014

Hi,

With "gtx refclk input" do you mean GTGREFCLK input which will be selected when CPLLREFCLKSEL[2:0] = 111? OR GTREFCLK[0/1]?

Thanks,
Shreyas

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Explorer
Explorer
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Registered: ‎12-18-2014

I do not exactly know what you mean but the ref clk will be connected to the IBUFDS_GTE2  buffer and its output to the gt_common.GTREFCLK0_IN input. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

HI ,

 

It is not recommended to use fabric clock for GT refclk input. You should be driving it from the board.

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Xilinx Employee
Xilinx Employee
5,728 Views
Registered: ‎07-21-2014
Hi,

you can directly take the differential clock in and connect it to the ports of IBUFDS_GTE2. as it is having differential inputs and this is recommended practice as Manusha said.
for more information on this primitive you can refer to below given UG page #33
http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf


Thanks,
Shreyas
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Explorer
Explorer
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Registered: ‎12-18-2014

As i said i will feed out the clock to a cleaner pll. 

The cleaner pll will attenuate the jitter and forward it to the transceiver.

 

FPGA_DIFF_CLK_OUT  ->  cleaner_pll  ->  FPGA_GTX_REFCLK_INPUT

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Professor
Professor
10,259 Views
Registered: ‎08-14-2007

If the clock you want to drive out is on a buffered clock net, then the best way is to instantiate an ODDR followed by an OBUFDS.  There should be examples of this if you search documentation for "clock forwarding."  You should also make sure that the LVDS output of the FPGA gives sufficient drive level to the jitter cleaner, and that the jitter cleaner provides sufficient drive for the GTX reference clock input.  Usually cap coupling is required in the GTX clock path, and depending on the drive style (LVPECL, CML... ) of the jitter cleaner you may need resistors to pull down and/or terminate the signal.

-- Gabor

View solution in original post