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Registered: ‎04-07-2020

Differential output options for HR pin at 1.8V? (XC7Z014S-CLG400)

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I want to output LVDS, but as I understand from https://www.xilinx.com/support/answers/43989.html (last two images), it is not possible unless I power the bank with 2.5V?

My first question:  really?  Am I really not missing anything?  I find this restriction quite absurd — although I can certainly choose the voltage, a voltage of 1.8V is already required at VCCAUX;  so, choosing 1.8V is advantageous because it saves me one LDO or switching regulator  (that is, for cases where I don't already have/need 2.5V for other reasons)

RSDS seems to have the same restriction, as per UG471, page 94.

My second question:  what differential output formats are available for this case?   I'm referring to the case of an HR IO pin from a bank that is powered with 1.8V.

Thanks,
Cal-linux
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Registered: ‎01-22-2015

Re: Differential output options for HR pin at 1.8V? (XC7Z014S-CLG400)

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@Cal-linux 

Yes, it is my understanding from AR#43989 and from UG471 that:

  1. You can output the IO Standard called LVDS_25 from an HR-bank with VCCO = 2.5V
  2. You can output the IO Standard called LVDS from an HP-bank with VCCO = 1.8V 

-and that neither LVDS nor LVDS_25 can be used for output from an HR-bank with VCCO=1.8V.

Table 1-55 in UG471 is a nice summary of the IO Standards for 7-Series devices.  It shows what bank-type and VCCO are needed for input and output of each IO Standard.   For example, you might be interested in DIFF_HSTL_I_18 and DIFF_HSTL_II_18, which be used for output from an HR bank with VCCO=1.8V.  See Table 12 of the datasheet, DS187, for your device to get details of these and other differential IO standards.

Be sure to read "Rules for Combining I/O Standards in the Same Bank" on page 97 of UG471(v1.10) when combining these lesser-used IO Standards with other IO Standards in the same bank of the FPGA.

Cheers,
Mark

 

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Registered: ‎01-22-2015

Re: Differential output options for HR pin at 1.8V? (XC7Z014S-CLG400)

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@Cal-linux 

Yes, it is my understanding from AR#43989 and from UG471 that:

  1. You can output the IO Standard called LVDS_25 from an HR-bank with VCCO = 2.5V
  2. You can output the IO Standard called LVDS from an HP-bank with VCCO = 1.8V 

-and that neither LVDS nor LVDS_25 can be used for output from an HR-bank with VCCO=1.8V.

Table 1-55 in UG471 is a nice summary of the IO Standards for 7-Series devices.  It shows what bank-type and VCCO are needed for input and output of each IO Standard.   For example, you might be interested in DIFF_HSTL_I_18 and DIFF_HSTL_II_18, which be used for output from an HR bank with VCCO=1.8V.  See Table 12 of the datasheet, DS187, for your device to get details of these and other differential IO standards.

Be sure to read "Rules for Combining I/O Standards in the Same Bank" on page 97 of UG471(v1.10) when combining these lesser-used IO Standards with other IO Standards in the same bank of the FPGA.

Cheers,
Mark

 

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