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Visitor
Visitor
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Registered: ‎09-19-2019

Differential signal input to PMOD

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Hi,

I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB. This differential signal will be an input to a buffer on the FPGA. The current xdc file on github uses LVCMOS33 as a default standard as shown below.

set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]

Would it be fine if I use LVCMOS33 or should I use another IO standard and if so which one should I use. I am using the Arty A7 100t board.

 

Thank you

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Registered: ‎06-21-2017

The 7 Series Select IO User Guide (UG471) says that for LVDS_25, the bank needs to be powered by 2.5V for outputs or if the internal differential termination is needed.  You can't change the voltage of the bank so you need to add a terminating resistor.  If you can find a way to place a 100 ohm resistor across the _p and _n signals at the pins that the signals enter the FPGA, LVDS_25 might work.  Be careful, a misconnection could damage the FPGA.

What frequency is this signal?  It would be safer to buy or make a boaard to plug into the PMOD to translate LVDS to a single ended signal.

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Registered: ‎06-21-2017

You would probably need to modify the board.  LVDS requires a 100 Ohm termination between the differential pair.  You cannot use the internal termination in the FPGA unless the bank is powered by 2.5V.  In addition, the PMOD inputs seem to be protected by 200 ohm in-line resistors according to the schematic I downloaded.  These would need to be replaced by zero ohm jumpers.  PMOD connectors aren't great for high speed signals and LVDS is meant for high speed signals.  The correct IO standard if you modify the terminations would be LVDS_25.

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Visitor
Visitor
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Registered: ‎09-19-2019

High Speed PMOD Arty A7 100tHigh Speed PMOD Arty A7 100t
PMOD JB schematicPMOD JB schematickjk

Hi bruce,

I plan on using the high speed PMOD on my board. The above pictures are from the reference manual and schematic of my board. I am new to FPGA's so I am not entirely sure if what they saying in the reference manual is what you are saying that I need on my board for the LVDS_25 IO standard to work. The problem I see is that the PMOD bank is powered by 3.3V VCC but the LVDS_25 requires 2.5V. So I am not entirely sure what to do.

Thank you

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Visitor
Visitor
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Registered: ‎09-19-2019
please ignore the kjk under the pictures
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Highlighted
684 Views
Registered: ‎06-21-2017

The 7 Series Select IO User Guide (UG471) says that for LVDS_25, the bank needs to be powered by 2.5V for outputs or if the internal differential termination is needed.  You can't change the voltage of the bank so you need to add a terminating resistor.  If you can find a way to place a 100 ohm resistor across the _p and _n signals at the pins that the signals enter the FPGA, LVDS_25 might work.  Be careful, a misconnection could damage the FPGA.

What frequency is this signal?  It would be safer to buy or make a boaard to plug into the PMOD to translate LVDS to a single ended signal.

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Teacher
Teacher
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Registered: ‎07-09-2009

You might get some more help on the digilent forum

they developed the arty

   and the PMOD "standard" and most of the PMOD boards,

https://forum.digilentinc.com/

 

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Visitor
Visitor
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Registered: ‎09-19-2019
Thanks for the help. The incoming signal is at a frequency of 4.092 MHz. I will take your advice and get another board to plug into the PMOD
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