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Visitor jeremieces
Visitor
10,669 Views
Registered: ‎07-08-2015

DisplayPort sink with SSC on a kintex-7 FPGA.

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Hi everyone, thanks for reading my post and thanks even more if you reply!

 

We designed a board with a kintex-7 FPGA that should act as a DisplayPort Sink (receiver). The connection between the FPGA and the DisplayPort transmitter (GPU) is direct (on the board).

I'm wondering how it is possible to receive a DisplayPort video stream with Spread Spectrum enabled (at 33Khz down-spread), and this without any component "sn65dp159" between the transmitter and the receiver.

 

Is the CDR of the kintex-7 GTX able to recover the input clock even if the input datas are sent with a down-spreaded clock?

(All this when the GTX is programmed for displayport operation).

 

I looked in the Kintex-7 Evaluation Board to see how it is done and I did conclude that:

 - In the document [1] it is explained that the kintex-7 evaluation board is working along with an FMC board called TB-FMCH-DP from Tokyo Electron Device.

 - In the user guide of the board (document [2]), I see that a component called "sn65dp159" is implemented on the board. And that this component is responsible for keeping signal integrity as swing level and jitter.

Does that mean that I need the sn65dp159 as an intermediaire component to depsread the datas?

 

Thus, my main question is: do I need a "sn65dp159" component between a displayport transmitter and receiver to despread the clock, or is it possible to have a direct connection. In that case, how is the FPGA able to recover the input datas that are down-spreaded?

 

Document reference:

[1]: http://www.xilinx.com/support/documentation/application_notes/xapp1178-displayport-transmit.pdf

[2]: http://solutions.inrevium.com/products/pdf/TB_FMCH_DP3_HWUserManual_1.00e.pdf

[3]: http://www.ti.com/lit/ds/symlink/sn65dp159.pdf

 

Thanks again for reading my post!

 

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Xilinx Employee
Xilinx Employee
20,442 Views
Registered: ‎07-31-2012

Re: DisplayPort sink with SSC on a kintex-7 FPGA.

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Hi jeremieces,

yes, you definitely have to use the re-timer DP159 which is specifically used for handling SSC clocking sources. All the latest DP core are supposed to use such a re-timer especially DP159 to handle such downspreaded clock sources.

We have a beta reference design on the KC705 board which you can find in our Display Port Lounge page, which is based on the TBDC-FMC3.1 FMC card which has the DP159 - http://www.xilinx.com/member/hdcp-dp-ref-design.html
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
3 Replies
Xilinx Employee
Xilinx Employee
20,443 Views
Registered: ‎07-31-2012

Re: DisplayPort sink with SSC on a kintex-7 FPGA.

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Hi jeremieces,

yes, you definitely have to use the re-timer DP159 which is specifically used for handling SSC clocking sources. All the latest DP core are supposed to use such a re-timer especially DP159 to handle such downspreaded clock sources.

We have a beta reference design on the KC705 board which you can find in our Display Port Lounge page, which is based on the TBDC-FMC3.1 FMC card which has the DP159 - http://www.xilinx.com/member/hdcp-dp-ref-design.html
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
Xilinx Employee
Xilinx Employee
10,623 Views
Registered: ‎07-31-2012

Re: DisplayPort sink with SSC on a kintex-7 FPGA.

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You can build upon this for your custom board along with the DP159 and this should help you handle SSC GPU's.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Visitor jeremieces
Visitor
10,605 Views
Registered: ‎07-08-2015

Re: DisplayPort sink with SSC on a kintex-7 FPGA.

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Thanks a lot for the answer!

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