03-14-2016 03:19 AM
I want to have document for XC7K325T-FFG676 (Kintex-7) in order to know the system to assign proper pins in XDC file. Basically, I have the XDC file for XC7K325T-FFG676. But I want to migrate to XC7K325T-FFG900 (Evaluation Kit). So I should first understand the pins of XC7K325T-FFG676. Then only I can change the XDC file XC7K325T-FFG900
03-14-2016 03:23 AM - edited 03-14-2016 03:24 AM
@sourajitjash Check package pins here for your package
Check the master xdc section for eval board xdc
03-14-2016 03:24 AM
You can refer below UG to know the banks organization etc of XC7K325T-FFG676 & FFG900
If you want the pin out please refer "ASCII Pinout Files" section
Hope this helps
03-14-2016 03:24 AM
03-14-2016 03:31 AM
I already have these documents. But I cannot know the excat board feature from pin locations and package files. What I want to look at the Clock module, the freq, pins for FFG676. That I cannot know from pin or package files. Basically I have one XDC file for FFG676. I want to understand the pins and how clock is connected. Then after knowing this, I will follow the same for FFG900
03-14-2016 03:33 AM
03-14-2016 03:36 AM
@sourajitjash You need to check the schematic of the board for how it is connected and to what. FFG676 is custom board and FFG900 is xilinx eval board. You can get the schematic of xilinx board here
03-14-2016 04:04 AM
03-14-2016 04:21 AM
I basically want to know clock source and frequency for ffg-676. I have all documents for ffg900. My XDC for FFG676 is connected to MRCC pins. MRCC pins can be connected to Clock signals?
03-14-2016 04:23 AM
03-14-2016 04:32 AM
Yes I have create_clocks.
There are two clokcs: one with time-period 5 ns is connected to Y23 of ffg676. Other with period: 200ns is connected to F17 of FFG676. So following pin location, you can get to know these are basically MRCC pins. Can you tell me whether Y23 and F17 are clock pins? So I can assign MRCC pins with similar votage and bank in FFG900. But how can I assure whether I have done the right thing?
03-14-2016 04:34 AM - edited 03-14-2016 04:36 AM
Yes both Y23 & F17 are MRCC pins (clock capable). Please look at http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg676pkg.txt
Have you designed your board? You should drive on-board clock oscillator output clocks to the respective pins you assign for FFG900 device.
03-14-2016 04:40 AM
Yes. Following that link, I found that they are MRCC pins. Can you tell me the functionality of MRCC pins?? From my understanding, I thought that clocks should be connetced to on-board oscillator. But here they are connected to MRCC pins. Following the http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg900pkg.txt, I assigned pin AD23 and L25 for FFG900. But How can assure whether I have done right.? In FFG900, the differential clock pins are AD12 and AD11. Similarly for FFG676, there should be differential system clocks. But in FFG676, clocks are connected to MRCC
03-14-2016 04:47 AM
03-14-2016 04:50 AM
I am migrating from ffg676 to KC705. Because I don;t have FFG676 package. KC-705 is FFG900.. For KC705, where should I connect my clocks? One of my clocks, has 200 MHz freq. But the other one is having less frequency
03-14-2016 09:00 AM
@sourajitjash What exactly are you trying to do? Are you trying to port a design from the custom board you have to KC705 eval board?
I hope you are aware that once you do all this, you will have to run your implementation again to make sure all your timing parameters and other constraints are met.