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Contributor
Contributor
12,334 Views
Registered: ‎10-06-2013

Document required for Kintex-7 ffg676 (XC7K325T-FFG676)

Hi,
I want to have document for XC7K325T-FFG676 (Kintex-7) in order to know the system to assign proper pins in XDC file. Basically, I have the XDC file for XC7K325T-FFG676. But I want  to migrate to XC7K325T-FFG900 (Evaluation Kit). So I should first understand the pins of XC7K325T-FFG676. Then only I can change the XDC file XC7K325T-FFG900

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Scholar
Scholar
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Registered: ‎06-05-2013

@sourajitjash Check package pins here for your package

http://www.xilinx.com/support/packagefiles/kintex-7-pkgs.htm

 

Check the master xdc section for eval board xdc

http://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf

-Pratham

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

@sourajitjash

 

You can refer below UG to know the banks organization etc of XC7K325T-FFG676 & FFG900

http://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

 

If you want the pin out please refer "ASCII Pinout Files" section 

 

Hope this helps

 

-Vanitha 

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Community Manager
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Registered: ‎07-23-2012

You can refer to UG475 for details on the packaging and pinout details of both devices.
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Contributor
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Registered: ‎10-06-2013

I already have these documents. But I cannot know the excat board feature from pin locations and package files. What I want to look at the Clock module, the freq, pins for FFG676. That I cannot know from pin or package files. Basically I have one XDC file for FFG676. I want to understand the pins and how clock is connected. Then after knowing this, I will follow the same for FFG900

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Community Manager
Community Manager
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Registered: ‎07-23-2012

In that case, why don't you create a I/O planning project in Vivado using xdc file and take it from there.
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Scholar
Scholar
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Registered: ‎06-05-2013

@sourajitjash You need to check the schematic of the board for how it is connected and to what. FFG676 is custom board and FFG900 is xilinx eval board. You can get the schematic of xilinx board here

https://secure.xilinx.com/webreg/clickthrough.do?cid=188020&license=RefDesLicense&filename=kc705_Schematic_xtp132_rev1_1.pdf&languageID=1

 

-Pratham

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Contributor
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Registered: ‎10-06-2013

From I/O planning projectm what information I can have?? And how much effort is needed for that? Any reference??

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Community Manager
Community Manager
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Registered: ‎07-23-2012

From pin planning, you will know which pins are used and what are the respective bank voltages.

If you want information on the frequency of clocks, terminations etc you will need the board schematics.
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Contributor
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Registered: ‎10-06-2013

I basically want to know clock source and frequency for ffg-676. I have all documents for ffg900. My XDC for FFG676 is connected to MRCC pins. MRCC pins can be connected to Clock signals?

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Community Manager
Community Manager
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Registered: ‎07-23-2012

In xdc, do you have create_clock constraints as well? If you have the timing constraints then you can get to know the frequency.
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Contributor
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Registered: ‎10-06-2013

Yes I have create_clocks.
There are two clokcs: one with time-period 5 ns is connected to Y23 of ffg676. Other with period: 200ns is connected to F17 of FFG676. So following pin location, you can get to know these are basically MRCC pins. Can you tell me whether Y23 and F17 are clock pins? So I can assign MRCC pins with similar votage and bank in FFG900. But how can I assure whether I have done the right thing? 

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Yes both Y23 & F17 are MRCC pins (clock capable). Please look at http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg676pkg.txt

 

Have you designed your board? You should drive on-board clock oscillator output clocks to the respective pins you assign for FFG900 device. 

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Contributor
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Registered: ‎10-06-2013

Yes. Following that link, I found that they are MRCC pins. Can you tell me the functionality of MRCC pins?? From my understanding, I thought that clocks should be connetced to on-board oscillator. But here they are connected to MRCC pins. Following the http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg900pkg.txt, I assigned pin AD23 and L25 for FFG900. But How can assure whether I have done right.? In FFG900, the differential clock pins are AD12 and AD11. Similarly for FFG676, there should be differential system clocks. But in FFG676, clocks are connected to MRCC

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Contributor
Contributor
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Registered: ‎10-06-2013

The XDC file for FFG676 has been generated from one Synopsys tool (ARChitect): Y23 and F17

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Community Manager
Community Manager
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Registered: ‎07-23-2012

MRCC/SRCC are clock capable IO pins and they have less skew. Please refer to Table 1-1 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf for details on MRCC and SRCC pins.

These pins are differential and if you want to drive a single ended clock signal then you have to make use of the P pin of the differential pair.

A clock from an external source drives these MRCC/SRCC pins. In case of KC705 (FFG900), we have on-board oscillator that generates 200 MHz clock and drives AD11/AD12 pins on board.

If you don't target KC705 then AD11/AD12 are as good as other MRCC pins to which you should source the clock.
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Contributor
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Registered: ‎10-06-2013

I am migrating from ffg676 to KC705. Because I don;t have FFG676 package. KC-705 is FFG900.. For KC705, where should I connect my clocks? One of my clocks, has 200 MHz freq. But the other one is having less frequency

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Moderator
Moderator
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Registered: ‎07-23-2015

@sourajitjash What exactly are you trying to do? Are you trying to port a design from the custom board you have to KC705 eval board?

 

If so,

  1. Do you completely understand the design since that would help you easily map the signals on KC705? 
  2. Do you have schematics of the custom board?
  3. If answer is yes to both the above, try understanding the xdc of the custom board by figuring out which signals were mapped to which pins. Once you have that understanding, it would be easy to remap them on KC705 for the same RTL design

I hope you are aware that once you do all this, you will have to run your implementation again to make sure all your timing parameters and other constraints are met. 

- Giri
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