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honghongrong
Visitor
Visitor
1,008 Views
Registered: ‎10-06-2018

Does center-aligned DDR RX using XAPP1017 design work?

    The xapp1017 is for edge-aligned DDR RX of source-synchronous LVDS interface. 

    The design inside uses IDELAYE2, BUFIO, BUFR primitives, thus leading to skew between the clk and the data path, right ?

    Does the design also work for center-aligned source-synchronous LVDS DDR interface without modifying the code?

    Thanks!

 

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10 Replies
drjohnsmith
Teacher
Teacher
999 Views
Registered: ‎07-09-2009

If I remember the Xapp, it moves a window around to find the edges,
as such it sounds like it wont work for centre aligned without modifications,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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honghongrong
Visitor
Visitor
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Registered: ‎10-06-2018

So how can I modify the code to support center-aligned DDR source synchronous input?

In serdes_1_to_468_idelay_ddr.v, I change the code:

            if (c_sweep_delay < {1'b0, bt_val[4:1]}) begin // choose the lowest delay value to minimise jitter
                        initial_delay <= c_sweep_delay + {1'b0, bt_val[4:1]} ;
           end
           else begin
                       initial_delay <= c_sweep_delay - {1'b0, bt_val[4:1]} ;
           end

 to:

        initial_delay <= c_sweep_delay;

 

but it doesn't work.

How to modify the code to support center-aligned rx?

Thanks!

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quis78
Observer
Observer
752 Views
Registered: ‎02-22-2017

Dear honghongrong,

did you solve this problem? I am facing a similar issue currently.

Best regards!

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el3ctrician
Observer
Observer
632 Views
Registered: ‎12-04-2018

Same issue here, any indications on how to use it with a center aligned interface ?  my first thoughts was to put another IDELAY2 before the block to bring my signal to Edge aligned but it seems very stupid and am not sure if two put in series can work together. A better approach would be to modify the process attached blow but i have no idea on which go where as it is not clear for me the whole concept of Dynamic Caption !
Any help will be very useful.

Thank

process (system_clk_int) begin							-- sweep data
if system_clk_int'event and system_clk_int = '1' then
	if su_locked = '0' then
		c_sweep_delay <= "00000" ;
		temp_shift <= (0 => '1', others => '0') ;
		clock_sweep_int <= (others => '0') ;
		zflag <= '0' ;
		not_rx_lckd_intd4 <= '1' ;
		rx_lckd_intd4 <= '0' ;
		initial_delay <= "00000" ;
	else 
		not_rx_lckd_intd4 <= not rx_lckd_intd4 ;
		if state2_count = "11111" then
			if c_sweep_delay /= bt_val then
		 		if zflag = '0' then
		 			c_sweep_delay <= c_sweep_delay + 1 ;
					temp_shift <= temp_shift(30 downto 0) & temp_shift(31) ;
				else
					zflag <= '0' ;
				end if ;
			else 
			 	c_sweep_delay <= "00000" ; 
			 	zflag <= '1' ;					-- need to check tap 0 twice bacause of wraparound
				temp_shift <= (0 => '1', others => '0') ;
			end if ;
			if zflag = '0' then
				if data_different = '1' then
					clock_sweep_int <= clock_sweep_int and not temp_shift ;
					if initial_delay = "00000" then
						rx_lckd_intd4 <= '1' ;
				  		if c_sweep_delay < '0' & bt_val(4 downto 1) then		-- choose the lowest delay value to minimise jitter
				  		 	initial_delay <= c_sweep_delay + ('0' & bt_val(4 downto 1)) ;
				  		else 
				  		 	initial_delay <= c_sweep_delay - ('0' & bt_val(4 downto 1)) ;
				  		end if ;
					end if ;
				else 
					clock_sweep_int <= clock_sweep_int or temp_shift ;
				end if ;
			end if ;
		end if ;
	end if ;
end if ;
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quis78
Observer
Observer
613 Views
Registered: ‎02-22-2017

@el3ctrician 

Actually the solution provided by @honghongrong together with a bitshift algorithm worked well for me in the end.

In my understanding after changing the initial delay the algorithm should work in the same way as before.

el3ctrician
Observer
Observer
569 Views
Registered: ‎12-04-2018

i already tried that with no luck, i gonna move on to a new question with more details about my specific interface. Thanks

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el3ctrician
Observer
Observer
511 Views
Registered: ‎12-04-2018

sorry @quis78 , would you please elaborate on the bitshift algorithm ? the bitshift I think will be used after the correct acquisition from the interface to align the word inside the parallel out of the ISERDES right ?

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quis78
Observer
Observer
505 Views
Registered: ‎02-22-2017

@el3ctrician 

Yes, after you made sure that you catch the individual bits in the middle of the eye the bitslip algorithm is applied to align the whole dataframe. So if you have 10-bit ADC for example and your MSB is bit b10 you make sure that the bits are aligned as b10 b9 ... b1 and not like b5 b4 ... b1 b10 b9 ... b6.

In my application I sample a clock signal coming from the ADC which is aligned with the data signals (same trace length on the PCB). Then if my the clock sample is 11110000 (in my application signal length is 8bit, the fast clock is 320MHz DDR i.e. sampling on both edges and the sample clock is 80MHz) I know that everything is fine. If it's for example 01111000 a bitslip is applied.

el3ctrician
Observer
Observer
491 Views
Registered: ‎12-04-2018

Thanks so much, did you enabled the dcd_correct and the phase detector or not ?

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quis78
Observer
Observer
478 Views
Registered: ‎02-22-2017

Yes, I enabled the phasedetector (needed for the dynamic capture in my understanding) but not dcd_correct.

Edit: Another thing I remember is that you have to wait for a few clock cycles after each bitslip.

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