cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
8,054 Views
Registered: ‎07-11-2008

Done pin did not go high

Hello,

 

when i tried to programm a Kintex-7 via slave serial mode the done pin did not go high.

It works when programming the FPGA via JTAG.

I've read a lot of answer records and data sheets, but nothing seems to help.

 

Here is the dump of the status register:

 

INFO:iMPACT - Current time: 19.05.2015 11:16:18
// *** BATCH CMD : ReadStatusRegister -p 1
Maximum TCK operating frequency for this device chain: 33000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading: -273.00 C
1: VCCINT Supply: Current Reading: 0.000 V
1: VCCAUX Supply: Current Reading: 0.000 V
'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 1
[1] FALLBACK_0 - FALLBACK TRIGGERED RECONFIGURATION : 0
[2] IPROG_0 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] WRAP_ERROR_0 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR : 0
[7] HMAC_ERROR_0 - HMAC ERROR : 0
[8] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[9] FALLBACK_1 - FALLBACK TRIGGERED RECONFIGURATION : 0
[10] IPROG_1 - INTERNAL WARMBOOT (IPROG) TRIGGERED RECONFIGURATION : 0
[11] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[12] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[13] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[14] WRAP_ERROR_1 - BPI FLASH ADDRESS COUNTER WRAP AROUND ERROR : 0
[15] HMAC_ERROR_1 - HMAC ERROR : 0
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] DECRYPTOR ENABLE : 0
[2] PLL LOCK STATUS : 1
[3] DCI MATCH STATUS : 1
[4] END OF STARTUP (EOS) STATUS : 1
[5] GTS_CFG_B STATUS : 1
[6] GWE STATUS : 1
[7] GHIGH STATUS : 1
[8] MODE PIN M[0] : 1
[9] MODE PIN M[1] : 1
[10] MODE PIN M[2] : 1
[11] INIT_B INTERNAL SIGNAL STATUS : 1
[12] INIT_B PIN : 1
[13] DONE INTERNAL SIGNAL STATUS : 1
[14] DONE PIN : 1
[15] IDCODE ERROR : 0
[16] SECURITY ERROR : 0
[17] SYSTEM MONITOR OVER-TEMP ALARM STATUS : 0
[18] CFG STARTUP STATE MACHINE PHASE : 0
[19] CFG STARTUP STATE MACHINE PHASE : 0
[20] CFG STARTUP STATE MACHINE PHASE : 1
[21] RESERVED : 0
[22] RESERVED : 0
[23] RESERVED : 0
[24] RESERVED : 0
[25] CFG BUS WIDTH DETECTION : 0
[26] CFG BUS WIDTH DETECTION : 0
[27] HMAC ERROR : 0
[28] PUDC_B PIN : 1
[29] BAD PACKET ERROR : 0
[30] CFGBVS PIN : 1
[31] RESERVED : 0

 

This looks like the startup sequence reaches the EOS state (Phase 7) and also reports that the done pin is high, but it isn't. when i measure it.

 

Hope somebody have any ideas.

 

Best regards,

 

Michael

0 Kudos
17 Replies
Highlighted
Xilinx Employee
Xilinx Employee
8,039 Views
Registered: ‎04-16-2012

Hello,

 

I observe that DONE PIN is HIGH from the status resgisters output.

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.
0 Kudos
Highlighted
Observer
Observer
8,035 Views
Registered: ‎07-11-2008

Hi,

 

you are right. The status register shows that DONE = HIGH, but when i measure the dine pin it is LOW,

and the FPGA isn't working.

Thats my problem.

 

Best regards,

 

Michael

0 Kudos
Highlighted
Scholar
Scholar
8,026 Views
Registered: ‎06-05-2013

@ifen_gmbh When you were configuring through JTAG did FPGA worked? 

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
8,022 Views
Registered: ‎07-11-2008

@pratham -> Yes. When i configure through JTAG the FPGA work.

 

-- michael

0 Kudos
Highlighted
Scholar
Scholar
8,015 Views
Registered: ‎02-27-2008

What is the state of the INIT_b pin?

 

If that is low, then there was an error in the bitstream, and the CRC did not match,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Observer
Observer
8,012 Views
Registered: ‎07-11-2008

@austin -> The INIT_b pin is HIGH.

0 Kudos
Highlighted
Scholar
Scholar
8,010 Views
Registered: ‎02-27-2008

What is the pullup resistor on the DONE PIN?

 

 

If the DONE goes high when programmed from JTAG, then I would expect it to go high with any other mode as well.

 

The temperature and internal voltages are incorrect, so that implies one or more of the power supplies are not working properly.

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Observer
Observer
8,006 Views
Registered: ‎07-11-2008

The pull-up resistor is 330Ohm

 

I will check the power supply again..

0 Kudos
Highlighted
Observer
Observer
7,981 Views
Registered: ‎07-11-2008

The power supplies are ok. I've cheked the voltage and the ramp time.

 

This:

1: Device Temperature: Current Reading: -273.00 C
1: VCCINT Supply: Current Reading: 0.000 V
1: VCCAUX Supply: Current Reading: 0.000 V

 

is also reported on an other board with a Kintex-7 which is working fine.

 

Best regards,

 

Michael

0 Kudos
Highlighted
Observer
Observer
7,197 Views
Registered: ‎07-11-2008

I have tied VCCADC_0 to GND because i dont want that the XADC draw any current because i don't t need its features.

 

But this schouldn't be a prroblem - right?

0 Kudos
Highlighted
Scholar
Scholar
7,190 Views
Registered: ‎02-27-2008

Correct,

 

That is just fine to do, but it confused me for a moment.

 

Look at the signal integrity of the configuration interface: rising and falling edges, look for riniging, over shoot, under shoot, etc.  Something about that mode is not working, where JTAG is working.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Observer
Observer
7,187 Views
Registered: ‎07-11-2008

I have an other Kintex-7 based board with excacty the same programming interface.

I've compared the CCLK and DIN signals and they look equal from the signal integrity point.

 

If there is any curruption on the configuration interface i expect to see this in the dump of the status register.

But from that point of view everything looks ok. The start-up FSM goes fine to Assert EOS and detects that the DONE pin is high (which isn't the case).

 

 

0 Kudos
Highlighted
Scholar
Scholar
7,175 Views
Registered: ‎02-27-2008

We are missing something important here,

 

Need to go back and review everything...

 

What mode are you using that isn't working?  Master mode serial?  Slave mode serial?  What cable are you using?  It may be your cable is ablke to do JTAG, but not able to do the serial programming (either it is broken, or it is not a supported interface)?

 

How is the bitstream generated?  What options are chosen?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Observer
Observer
7,159 Views
Registered: ‎07-11-2008

Ok - i will try to explain the setup(s) a little more detailed.

 

I have two Kintex-7 (XC7K160T-FBG676) based boards (A) and (B)  developed by myself.

Board (A) (>30pcs) is working since a year. The FPGA is programmed in slave serial mode via a microcontroller.

The new board (B) (2pcs) do it exactly the same way but include some minor changes on the power supply and other not FPGA related components.

 

The bitfile was generated by Vivado 2014.4 with default options. The bitfile is loaded on board (A) via microcontroller without any problem. The same bitfile is used on board (B).

 

For JTAG programming i use the Platform USB cable (DLC9).

When programing via JTAG the DONE pin went high and the FPGA work fine.

 

Best regards,

 

Michael

0 Kudos
Highlighted
Moderator
Moderator
7,152 Views
Registered: ‎01-15-2008

are you using any IOstandards with DCI? 

in the B board can you try to send some more CCLK from controller after the data load is completed

Following Application notes might help

http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf

 

--Krishna

Highlighted
Observer
Observer
7,145 Views
Registered: ‎07-11-2008

Yeah - DCI was the problem.

 

BITSTREAM.STARTUP. MATCH_CYCLE = AUTO

--> When the Auto setting is specified,
write_bitstream searches the design for any DCI I/O
standards. If DCI standards exist, write_bitstream
uses BITSTREAM.STARTUP.MATCH_CYCLE=2.

 

but why does the status register report that everything is ok?

0 Kudos
Highlighted
Observer
Observer
6,927 Views
Registered: ‎07-11-2008

Any ideas?

0 Kudos