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Registered: ‎03-17-2020

EQUALIZATION selection for LVDS input to HP bank, AC coupling. UG571

Hi, 

In UG571, table 1-56, it indicates the combination for LVDS termincation if I use internal termination DIFF_TERM.

My question is:

If the signal is diff pair clock input tp HP bank, and external AC coupling (without external Bias), how should I select them?

I guess I need set DIFF_TERM=TRUE ; DQS_BIAS = TRUE. But should I must select EQUALIZATION = EQ_LEVEL0~4? Seems I cannot select EQ_NONE if we see this table 1-56.

Correct?

 
 

Table 1-56: Allowed Combinations of DQS_BIAS and EQUALIZATION (HP I/O Banks)
Coupling         DQS_BIAS               Equalization
AC coupling    FALSE or TRUE      EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4
DC coupling    FALSE                     EQ_NONE

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Registered: ‎01-22-2015

Re: EQUALIZATION selection for LVDS input to HP bank, AC coupling. UG571

@EWENFEN 

Welcome to the Forum!

If the signal is diff pair clock input tp HP bank, and external AC coupling (without external Bias), how should I select them?

As you say, Tables 1-55 and 1-56 in UG571(v1.12) indicate the needed settings.  You should set DIFF_TERM=TRUE,  DQS_BIAS=TRUE, and EQUALIZATION=EQ_LEVEL0~4.  You cannot use EQUALIZATION=EQ_NONE when DQS_BIAS=TRUE.   As shown in UG912(v2019.1), pages 207, 201, 188, you can set these properties by placing constraints like the following in the project .xdc file.

set_property EQUALIZATION EQ_LEVEL0 [get_ports CLK_P]
set_property DQS_BIAS TRUE [get_ports CLK_P]
set_property DIFF_TERM_ADV TERM_100 [get_ports CLK_P]

Also, check the datasheet for your device to ensure that your LVDS input meets the VIDIFF and VICM_AC specifications (eg. see Table 19 in DS892(v1.18)).

Finally, note that AC-coupling of LVDS is suitable for clock signals but is generally not suitable for data signals because AC-coupling cannot pass a data value that is constant.

Cheers,
Mark

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