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2,949 Views
Registered: ‎03-03-2017

ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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I am working on a design in Vivado 2018.1 where I want to use LVDS_25 IOSTANDARD on a pin pair that is placed in a 3.3V bank which should work according to AR 43989 if I set DIFF_TERM to false.

Below is the error in the implementation log file:

Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13. For example, the following two ports in this bank have conflicting VCCOs:  
SCL_RX_HDMI_DP159 (LVCMOS33, requiring VCCO=3.300) and HS88_EDP_AUX_P (LVDS_25, requiring VCCO=2.500)

Here is the XDC definning the two pins that the error is complaining about:

set_property -dict {IOSTANDARD LVDS_25  PACKAGE_PIN N21 DRIVE 16 DIFF_TERM FALSE}   [get_ports HS88_EDP_AUX_P];
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN N26 DRIVE 16}                   [get_ports SCL_RX_HDMI_DP159];

I opened the synthesized design and verified that DIFF_TERM was correctly set to false:

get_property DIFF_TERM [get_ports HS88_EDP_AUX_P]
0


Any ideas what I am doing wrong here?

 

Thanks.

Tim

 

1 Solution

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Moderator
Moderator
3,110 Views
Registered: ‎07-23-2015

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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@tim_severance From what I see on your test design, you are assigning LVDS_25 to an Output in a 3.3V Bank which is not allowed and hence the tool complains. 

 

You can have LVCMOS33 (Input or Output)  in a Bank and "only" have LVDS_25 as an input (IBUFDS not OBUFDS) in the same bank. The AR you referred to mentions the same. DIFF_TERM is applicable for inputs and not Outputs. 

 

As a test, you can make HS88_EDP_AUX_P/N an input in your design, you will not see the DRC. 

 

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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View solution in original post

7 Replies
2,936 Views
Registered: ‎03-03-2017

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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As an example I setup a very simple project in Vivado 2018.1 with the following files and got the same exact error:

 

Project setup with xc7k160tffg676-1:

dummy_top.v:

module dummy_top(
    output dummy1_N,
    output dummy1_P,
    input dummy2
    );
    
    OBUFDS OBUFDS_inst (
        .O(dummy1_P),     // 1-bit output: Diff_p output (connect directly to top-level port)
        .OB(dummy1_N),  // 1-bit output: Diff_n output (connect directly to top-level port)
        .I(dummy2)    // 1-bit input: Buffer input
        );

endmodule

constr.xdc:

set_property -dict {IOSTANDARD LVDS_25  PACKAGE_PIN N22 DIFF_TERM FALSE}   [get_ports dummy1_N];
set_property -dict {IOSTANDARD LVDS_25  PACKAGE_PIN N21 DIFF_TERM FALSE}   [get_ports dummy1_P];
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN N26 DRIVE 16}          [get_ports dummy2];

Errors when running implementation:

errors.png

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2,911 Views
Registered: ‎03-03-2017

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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Another piece of information:

 

If I tell Vivado to ignore BIVC-1 DRC by adding the below to the constr.xdc file I get the following errors.

 

XDC addition:

set_property IS_ENABLED 0           [get_drc_checks BIVC-1];

Errors:

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-372] Bank.13 has terminals with incompatible standards:
Incompatible Pair of IO Standards: LVCMOS33 and LVDS_25
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  In   Bank: 13 Placed :
	Term: dummy2
SioStd: LVDS_25    VCCO = 2.5 Termination: 0  TermDir:  Out  Bank: 13 Placed LVDS :
	Term: dummy1_P
	Term: dummy1_N


ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 12 |    50 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |    50 |     3 | LVCMOS33(1)  LVDS_25(2)                                                |                                          |        |  +2.50 |    YES |     |
| 14 |    50 |     0 |                                                                        |                                          |        |        |        |     |
| 15 |    50 |     0 |                                                                        |                                          |        |        |        |     |
| 16 |    50 |     0 |                                                                        |                                          |        |        |        |     |
| 32 |    50 |     0 |                                                                        |                                          |        |        |        |     |
| 33 |    50 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    50 |     0 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   400 |     3 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 13     | dummy1_P             | LVDS_25         | IOB_X0Y76            | N21                  |                      |
|        | dummy1_N             | LVDS_25         | IOB_X0Y75            | N22                  |                      |
|        | dummy2               | LVCMOS33        | IOB_X0Y90            | N26                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 121f09e51

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1081.402 ; gain = 12.434
Phase 1 Placer Initialization | Checksum: 121f09e51

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1081.402 ; gain = 12.434
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 121f09e51

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1081.402 ; gain = 12.434
36 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Wed Jun  6 13:59:37 2018...
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Xilinx Employee
Xilinx Employee
2,888 Views
Registered: ‎05-08-2012

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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Hi @tim_severance. Can you try not setting DIFF_TERM to FALSE? FALSE is the default value.

 

One way to test this without re-running synthesis would be to run the following commands after the failure.

 

reset_property DIFF_TERM [get_ports HS88_EDP_AUX_P]

place_design

 

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2,879 Views
Registered: ‎03-03-2017

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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Hi @marcb,

   I reran implementation with the constraint file below and got the same results.

#set_property DIFF_TERM FALSE        [get_ports dummy1_N];
set_property IOSTANDARD LVDS_25     [get_ports dummy1_N];
set_property PACKAGE_PIN N22        [get_ports dummy1_N];

#set_property DIFF_TERM FALSE        [get_ports dummy1_P];
set_property IOSTANDARD LVDS_25     [get_ports dummy1_P];
set_property PACKAGE_PIN N21        [get_ports dummy1_P];

set_property IOSTANDARD LVCMOS33    [get_ports dummy2];
set_property PACKAGE_PIN N26        [get_ports dummy2];
set_property DRIVE 16               [get_ports dummy2];

#set_property IS_ENABLED 0 [get_drc_checks {BIVC-1}]

   As far as doing the reset and place_design wouldn't I have to have an implemented design opened to do that?

Thanks.

Tim

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2,768 Views
Registered: ‎03-03-2017

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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@marcb,  Any updates on this?   This should be possible according to AR43989.   Is this a bug in Vivado 2018.1?

Thanks.

Tim

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Moderator
Moderator
3,111 Views
Registered: ‎07-23-2015

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

Jump to solution

@tim_severance From what I see on your test design, you are assigning LVDS_25 to an Output in a 3.3V Bank which is not allowed and hence the tool complains. 

 

You can have LVCMOS33 (Input or Output)  in a Bank and "only" have LVDS_25 as an input (IBUFDS not OBUFDS) in the same bank. The AR you referred to mentions the same. DIFF_TERM is applicable for inputs and not Outputs. 

 

As a test, you can make HS88_EDP_AUX_P/N an input in your design, you will not see the DRC. 

 

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

2,753 Views
Registered: ‎03-03-2017

Re: ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13

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@gnarahar,

   Oh thank you, that is the piece I was missing.   So what I am trying to do is not possible then.

Thanks.

Tim

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