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Registered: ‎08-15-2014

ERROR: [Place 30-126] Unroutable Placement! A BUFIO can only drive loads in the same IO bank.

hi, I met below errors:

ERROR: [Place 30-126] Unroutable Placement! A BUFIO can only drive loads in the same IO bank. The following BUFIO clock loads are placed too far from t he BUFIO to be routable.
669 u_NV_hstdm_bank_receieve_AB/pinmux_rx_bus[1].i_dnlvds_pinmux_rx/gen_source_synchronous_clock.i_ibufio_clk_iserdes_2x (BUFIO.O) is provisionally placed by clockplacer on BUFIO_X1Y35 (in SLR 2)
670 The loads are distributed to 1 user pblock constraints. In addition, there are 20 loads not in user pblock constraints.
672 Displaying only the first 20 or fewer instances under each constraint as list of loads is too long
674 Displaying first 20 loads not in user pblock constraint:
675 u_NV_hstdm_bank_receieve_AB/pinmux_rx_bus[1].i_dnlvds_pinmux_rx/io[1].i_dnlvds_pinmux_rx_iserdes/gen_monitor.i_iserdes_monitor (ISERDESE2.CLK) is locked to ILOGIC_X1Y471 (in SLR 3)
676 u_NV_hstdm_bank_receieve_AB/pinmux_rx_bus[1].i_dnlvds_pinmux_rx/io[1].i_dnlvds_pinmux_rx_iserdes/i_iserdes_master (ISERDESE2.CLK) is locked to ILOGIC_X1Y472 (in SLR 3)

Here is the clock archteicture in my code. 

I checked my constraints, actually below CLK_P anc CLK_IN pins are assigned  to SLR3 actually.

Since the input of IBUFDS is in SLR3, I don't understand why it is reporting IBUFDS.O in SLR2 now? 

IBUFDS #(.DIFF_TERM("TRUE")) i_ibufds_clk_iserdes_2x ( .I(CLK_P), .IB(CLK_N), .O(clk_iserdes_2x_ibufds) );
BUFIO i_ibufio_clk_iserdes_2x ( .I(clk_iserdes_2x_ibufds), .O(clk_iserdes_2x));
BUFR #(.BUFR_DIVIDE(BUFR_DIVIDE_STR)) i_ibufr_clk_iserdes ( .I(clk_iserdes_2x_ibufds), .O(clk_iserdes), .CE(1'b1), .CLR(1'b0));

set_property PACKAGE_PIN M20 [get_ports {BANK_CLKIN_AB0_P}]
553 set_property PACKAGE_PIN L20 [get_ports {BANK_CLKIN_AB0_N}]

attaced detailed log.

Rule Description: An IO driving a BUFR must both be placed in the same clock region
725 u_NV_hstdm_bank_receieve_AB/pinmux_rx_bus[1].i_dnlvds_pinmux_rx/gen_source_synchronous_clock.i_ibufds_clk_iserdes_2x (IBUFDS.O) is provisionall y placed by clockplacer on IOB_X1Y428 (in SLR 2)
726 u_NV_hstdm_bank_receieve_AB/pinmux_rx_bus[1].i_dnlvds_pinmux_rx/gen_source_synchronous_clock.i_ibufr_clk_iserdes (BUFR.I) is provisionally plac ed by clockplacer on BUFR_X1Y36 (in SLR 3)
727 ERROR: The above is also an illegal clock rule
728 Workaround: < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_NV_hstdm_bank_receieve_AB/pinmux_rx_bus[1].i_dnlvds_pinmux_rx/clk_iserdes_2x _ibufds] >

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