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Anonymous
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ERROR: [Place 30-574] Sub-optimal placement

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Device : v72000T1925 -1

Design description: slow clock input in a non-cc pin(AM34).with about 700 loads.BUFG or BUFH inserted.

Netlist:

  IOBUF xilinx_pad_inst ( .O(jtck_c), .IO(JTCK), .I(GND), .T(VCC)

);

  BUFG xilin_bufg_inst(.I(jtck_c),.O(jtck_o));

FDP fdp1(

               .C(jtck_o),

               ...

Error message:

Phase 7.1 IO & Clk Placer & Init ERROR: [Place 30-574] Sub-optimal placement for a clock-capable IO pin and BUFG pair. No CLOCK_DEDICATED_ROUTE constraint override is possible on internal macros or primitives. Please convert the internal macros or primitives to independent instances if you wish to enable the CLOCK_DEDICATED_ROUTE constraint for this connection

xilinx_pad_inst/IBUF (IBUF.O) is locked to IOB_X0Y105 (in SLR 0)  xilinx_pad_inst_cb (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y27 (in SLR 0)

The above error could possibly be related to other connected instances. Following is a list of  all the related clock rules and their respective instances.

Clock Rule: rule_multi_slr_bufg  Rule Description: For a multi-SLR device, a maximum of one BUFG at same relative position in different  SLRs can be used, that is two BUFG sites  whose Y-index differs by a multiple of 32 cannot be used  at the same time  xilinx_pad_inst_cb (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y27 (in SLR 0)

Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO is placed on a CCIO pin (b) The BUFG is placed in the same half of the SLR as the CCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.

         I have tried some way:

1. Replace the BUFG with BUFH. and set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTCK]

fail:

ERROR: [Place 30-169] Sub-optimal placement for a clock-capable IO pin and BUFH pair. No CLOCK_DEDICATED_ROUTE constraint override is possible on internal macros or primitives. Please convert the internal macros or primitives to independent instances if you wish to enable the CLOCK_DEDICATED_ROUTE constraint for this connection

 

                xilinx_pad_inst/IBUF (IBUF.O) is locked to IOB_X0Y105 (in SLR 0)

                xilinx_pad_inst_cb (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X0Y24 (in SLR 0)

Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO is placed on a CCIO pin (b) The BUFH is placed in the same clock region row as the CCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.

2.set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtck_c]

fail

 

Can you give me advice to route this design?

 

1 Solution

Accepted Solutions
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Xilinx Employee
Xilinx Employee
29,940 Views
Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hello,

 

I created a small test case to recreate the error IOBUF(O pin) --> BUFG--> FDCE. In vivado 2012.4 I got the same error message as yours.

 

In vivado 2013.2, the error message is as below:

ERROR: [Place 30-574] Sub-optimal placement for a clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets O_1] >

IOBUF_inst/IBUF (IBUF.O) is locked to IOB_X0Y140 (in SLR 0)
BUFG_inst (BUFG.I) is locked to BUFGCTRL_X0Y54 (in SLR 1)

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_multi_slr_bufg
Rule Description: For a multi-SLR device, a maximum of one BUFG at same relative position in different
SLRs can be used, that is two BUFG sites whose Y-index differs by a multiple of 32 cannot be used
at the same time
BUFG_inst (BUFG.O) is locked to BUFGCTRL_X0Y54 (in SLR 1)

Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO-capable site (b) The BUFG is placed in the same half of the device or SLR as the CCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
Phase 1.8 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15d0c53fe

 

In both cases (2012.4 and 2013.2), when I applied CLOCK_DEDICATED_ROUTE FALSE on input of BUFG, it worked.

 

Can you post IOBUF--> BUFG schematic of your case so that we can check further.

 

I have attached the test case for your reference. Uncomment line 3 in XDC to overcome the error in testcase.

 

Also check the warnings in the log file (jst to ensure that the tool is able to pick the CLOCK_DEDICATED_ROUTE constraint in XDC).

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
21,680 Views
Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi,

 

Regarding the first error which you were facing IO and BUFG pair. If you want to degrade the error to warning message you can try to place CLOCK_DEDICATED_ROUTE = FALSE constraint on BUFG (instance in the error message) input in XDC as below:

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtck_c]

 

or

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins xilinx_bufg_inst/I]

 

In order to use the dedicated path as the error message says you need to lock the IO to CCIO pin and ensure that the BUFG is placed in the same half of the SLR.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Anonymous
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Re: ERROR: [Place 30-574] Sub-optimal placement

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Thank you for your quick response.

I tried CLOCK_DEDICATED_ROUTE = FALSE and then BUFH with CLOCK_DEDICATED_ROUTE = FALSE but both failed.

 

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Anonymous
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Re: ERROR: [Place 30-574] Sub-optimal placement

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and the error message said " No CLOCK_DEDICATED_ROUTE constraint override is possible on internal macros or primitives". What is internal macros or primitives?
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi,

 

The macro IOBUF gets translated into its component parts IBUF and OBUFT. In this case seperate IBUF & OBUFT components would need to be instantiated instead of the IOBUF to apply CLOCK_DEDICATED_ROUTE property or you can use the constraint on the input of BUFG.

 

Can you try below:

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtck_c]

 

or

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins xilinx_bufg_inst/I]

 

Thanks,

Deepika.

Thanks,
Deepika.
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Anonymous
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Re: ERROR: [Place 30-574] Sub-optimal placement

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i have tried set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtck_c](you can see from my post) and failed.
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Xilinx Employee
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Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Ok, from the post i thought you have applied it on JTCK. Can you once try applying it on I pin of BUFG? 

Thanks,
Deepika.
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Anonymous
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Re: ERROR: [Place 30-574] Sub-optimal placement

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in my post in can see :
I have tried some way:

1. Replace the BUFG with BUFH. and set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTCK]
fail
2.set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtck_c]

fail
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Xilinx Employee
Xilinx Employee
29,941 Views
Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hello,

 

I created a small test case to recreate the error IOBUF(O pin) --> BUFG--> FDCE. In vivado 2012.4 I got the same error message as yours.

 

In vivado 2013.2, the error message is as below:

ERROR: [Place 30-574] Sub-optimal placement for a clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets O_1] >

IOBUF_inst/IBUF (IBUF.O) is locked to IOB_X0Y140 (in SLR 0)
BUFG_inst (BUFG.I) is locked to BUFGCTRL_X0Y54 (in SLR 1)

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_multi_slr_bufg
Rule Description: For a multi-SLR device, a maximum of one BUFG at same relative position in different
SLRs can be used, that is two BUFG sites whose Y-index differs by a multiple of 32 cannot be used
at the same time
BUFG_inst (BUFG.O) is locked to BUFGCTRL_X0Y54 (in SLR 1)

Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO-capable site (b) The BUFG is placed in the same half of the device or SLR as the CCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
Phase 1.8 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15d0c53fe

 

In both cases (2012.4 and 2013.2), when I applied CLOCK_DEDICATED_ROUTE FALSE on input of BUFG, it worked.

 

Can you post IOBUF--> BUFG schematic of your case so that we can check further.

 

I have attached the test case for your reference. Uncomment line 3 in XDC to overcome the error in testcase.

 

Also check the warnings in the log file (jst to ensure that the tool is able to pick the CLOCK_DEDICATED_ROUTE constraint in XDC).

 

Thanks,

Deepika.

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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View solution in original post

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Anonymous
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21,625 Views

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi Deepika:

          The sch is in the attachment and it is quite simple.What i have doubt is that it is said CLOCK_DEDICATED_ROUTE is not possible in my log and it "may" be routable in your error log. I want to know what is "internal macros or primitives".

iobuf.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi,

 

Please check the project attachment i have added in my ealier email (use vivado 2012.4). I have recieved the same error (not possible in log) but I was able to overcome it using CLOCK_DEDICATED_ROUTE from XDC. 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Anonymous
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Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi Deepika:

       I tried your design project file and the CLOCK_DEDICATED_ROUTE worked well. Then i tried to set a location constraints set_property LOC BUFGCTRL_X0Y0 [get_cells xilinx_pad_inst_cb] acompany with the set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins jtck_c]. The error is degraded into a warning. Thank you for you help!

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Xilinx Employee
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Registered: ‎09-20-2012

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hello,

 

Good to hear that it works now.

 

Please mark the post which helped you as solution so that it will be helpful for other users.

 

Regards,

Deepika.

Thanks,
Deepika.
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Registered: ‎05-29-2014

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi,

I am getting this error and I want to fix it instead of converting it to a warning. I couldn't find any procedure fixing the error with online search. What is the proper steps for that? 

 

Here is my error :

 

 

ERROR: [Place 30-574] Sub-optimal placement for a clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets top0/pad_module/phy_fmc_hpc_hb_in_32] >

top0/pad_module/FMC_IOBUF_091/IBUF (IBUF.O) is locked to IOB_X0Y26 (in SLR 0)
top0/ulpi0_clk_bufg1 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31 (in SLR 0)

 

 


After reading this thread, I added the following constraint :

 

 

set_property LOC BUFGCTRL_X0Y26 [get_cells top0/ulpi0_clk_bufg1]

The constraint was accepted as you can see from the report below, but I still get the same error.

ERROR: [Place 30-574] Sub-optimal placement for a clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets top0/pad_module/phy_fmc_hpc_hb_in_32] >

top0/pad_module/FMC_IOBUF_091/IBUF (IBUF.O) is locked to IOB_X0Y26 (in SLR 0)
top0/ulpi0_clk_bufg1 (BUFG.I) is locked to BUFGCTRL_X0Y26 (in SLR 0)


Am I doing something wrong? This is on virtex 7 and the problem pin is location is AY40.

If there are more discussions/documents on the trade off between dedicated route FALSE/TRUE, please point me to it. I think I want to use dedicated route TRUE in this case, it's a high frequency clock with paths to other IO signals.

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Registered: ‎02-04-2014

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi ,

 

By using the set_property attribure in the xdc file , the PnR run completes,

but  it takes very long run times (if more set_property attribures added in tbe xdc file) and results in  poor timing performance.

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtck_c]

 

Please suggest any solution for removing the ERROR instead of reducing the severity to WARNING.

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Xilinx Employee
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Re: ERROR: [Place 30-574] Sub-optimal placement

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> Please suggest any solution for removing the ERROR instead of reducing the severity to WARNING.

 

Fix your board so that the clock input comes in on a the correct pin.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Registered: ‎11-12-2010

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hello there.

 

I am a newbee with virtex7. I used to work with spartan3 long time back.

 

I am using XC7VX690T-2FFG1761. I am getting similar warning. In on the message from Deepika, she mentioned the other person to fix the board so that the clock comes on the right pin.

 

How do I know which pin is the right pin for the clock. On spartan-3, there used to be a  special pin called Global clock pin whcih could be used for clock inputs but I do not see similar name here. So I dont know which pin I should use for clock input.

 

 

*************

XDC file: (I randomly selected some pins.)

 

# port reset_n
set_property PACKAGE_PIN A24 [get_ports {reset_n}]
set_property IOSTANDARD LVCMOS18 [get_ports {reset_n}]
#set_property PULLUP true [get_ports {reset_n}]

# port clkin
set_property PACKAGE_PIN A25 [get_ports {clkin}]
set_property IOSTANDARD LVCMOS18 [get_ports {clkin}]
#set_property PULLUP true [get_ports {clkin}]

# port clkout
#set_property PACKAGE_PIN BB26 [get_ports {clkin}]
set_property IOSTANDARD LVCMOS18 [get_ports {clkin}]
#set_property PULLUP true [get_ports {clkin}]

# port output1
#set_property PACKAGE_PIN BB27 [get_ports {output1}]
set_property IOSTANDARD LVCMOS18 [get_ports {output1}]
#set_property PULLUP true [get_ports {output1}]

# port output2
#set_property PACKAGE_PIN BB29 [get_ports {output2}]
set_property IOSTANDARD LVCMOS18 [get_ports {output2}]
#set_property PULLUP true [get_ports {output2}]

 

*****
Error:

ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets n_1_n_0_clkin_IBUF_inst_BUFG_inst] >

clkin_IBUF_inst (IBUF.O) is locked to IOB_X1Y397
n_0_clkin_IBUF_inst_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
Phase 2.1.5.2 IO & Clk Clean Up | Checksum: 1ec1c170

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Xilinx Employee
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Re: ERROR: [Place 30-574] Sub-optimal placement

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The 7 Series Clocking user guide describes the various input options for clcks and the resources that they can connect with and the 7 Series Package and Pinout user guide documents the pin naming conventions so that you can correctly assign the clock inputs.
------Have you tried typing your question into Google? If not you should before posting.
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Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi,

 

Im having a similar problem (using Vivado 2014.3 and Artix-7).  I have a clock coming in on a SRCC pin to the device and am then instantiating an IBUFG.  I get the sub-optimal placement error. 

 

I would have expected the tool to select a bufg that the SRCC pin can route to directly, but this appears not to be the case.  I'd like to constrain the location of the BUFG to ensure it is in the same half of the design as the pin and can use dedicated routing. 

 

Where can I find out what the BUFG locations are and which are are top and bottom?  i.e. if i want to do "set_property LOC BUFG ...." what are the options for BUFG XY and how do these map onto the device?  The clocking resource user guide does not have this level of detail.

 

Liz

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Re: ERROR: [Place 30-574] Sub-optimal placement

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I have found the issue with my design.  I was bringing the clock into the srcc n pin rather than the p pin, hence could not access the BUFG.  I will move the clock pin to rectify this.

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Registered: ‎05-26-2015

Re: ERROR: [Place 30-574] Sub-optimal placement

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Try to instantiate BUFR from language template and use the output of that as a clk.

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Registered: ‎07-23-2014

Re: ERROR: [Place 30-574] Sub-optimal placement

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Hi folks,

I 've faced the same issue because

a single ended clock has been placed on the N-Side of a differential pair CCIO-pin

It is not possible to move the clock on the board to the

P-Side of a differential pair CCIO-

And setting

set_property CLOCK_DEDICATED_ROUTE FALSE

is not satisfying due to unstable behaviour.

Is it possible to fix the issue apart from changing the PCB?

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Xilinx Employee
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Re: ERROR: [Place 30-574] Sub-optimal placement

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You need to change the PCB to have the clock connected to the right pin in order to use the dedicated routing.

------Have you tried typing your question into Google? If not you should before posting.
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Re: ERROR: [Place 30-574] Sub-optimal placement

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I get it, thanx.
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Xilinx Employee
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Re: ERROR: [Place 30-574] Sub-optimal placement

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Single ended clocks need to be placed on the P-side of the clock pin pair. See Clockin User guide (below). I think it's mentione in several places. The N-side will cause a local route to the clock resource (MMCM, PLL or BUFG). Makes timing closer difficult and add Jitter amoung other things.

 

"Single-ended clock inputs must be assigned to the P (master) side of the clock-capable

input pin pair.

If a single-ended clock is connected to the P-side of a differential clock pin pair, the N-side

cannot be used as another single-ended clock pin—it can only be used as a user I/O. For

pin naming conventions, refer to UG475, 7 Series FPGA Packaging and Pinout Specification"

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